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Handout #1 |
Course Information ( PDF ) |
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Handout #2 |
Syllabus ( PDF ) |
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Handout #3 |
Homework, Project and Exam Schedule ( PDF ) |
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Handout #4 |
Questionnaire ( PDF ) |
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Handout #5 |
The Quine-McCluskey Method ( PDF ) |
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Lecture #1: Slides ( PDF ) |
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Handout #6 |
Multi-Output Functions (hardcopy only)* |
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Handout #7 |
Heuristic Minimization of Two-Level Circuits (hardcopy only)* |
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Handout #8 |
Rick Rudell's PhD Thesis: Chapters 1 and 2 ( PDF ) |
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Lecture #2 (part 1): Slides ( PDF ) |
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Lecture #2 (part 2): Slides ( PDF ) |
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Handout #9 |
Homework #1 (PDF ) |
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Handout #9a |
Homework #1, Problem #1 (TXT ) (Getting Started with SIS ) |
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Handout #10 |
Heuristic Two-Level Logic Minimization (hardcopy only)* |
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Handout #11 |
Overview of Tautology Checking (PDF ) |
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Handout #12 |
Handout of Examples (PDF ) |
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Lecture #3: Slides ( PDF ) |
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Handout #13 |
Homework #2 (PDF ) |
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Handout #14 |
Selected Problems (ch. 5.8) (hardcopy only)* |
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Handout #15 |
Homework #1 Solutions (hardcopy only)* |
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Handout #16 |
Overview of Fast Complementation (PDF ) |
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Handout #17 |
Rudell's Master's thesis (UC Berkeley): chs. 4.7-4.8 Last-gasp, super-gasp, make-sparse (PDF ) |
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Handout #18 |
Overview of Fast Prime Generation (PDF ) |
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Handout #19 |
Prime Generation Problem Example (PDF ) |
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Handout #20 |
Homework #3 ( WITH CORRECTED PROBLEM #5!) (PDF ) |
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Lecture #5: Slides ( PDF ) |
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Handout #21 |
Homework #2 Solutions (hardcopy only)* |
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Lecture #6: Slides ( PDF ) |
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Handout #22 |
Kernels, Co-Kernels and Extraction Examples (PDF ) |
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Handout #23, #23(a-e) |
#23 Midterm Homework and CAD Project ( PDF ) #23a Midterm CAD Project, Part #1: Designing a Single-Cube Extraction Tool for Multi-Level Optimization ( TXT ) #23b Midterm CAD Project, Part #2: Unate Recursive Paradigm -- Function "Similarity" Evaluation Tool ( TXT ) #23c Introduction to the SIS CAD Package: Multi-Level Logic Optimization ( TXT ) #23d Midterm CAD Project, Part #2: Input/Output Format and Program Requirements ( TXT ) #23e Writeup, Submission and Demo Information ( TXT ) [also includes a sample benchmark + solution] |
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Handout #24 |
Basic Tree-Based Covering Example (area-oriented) (PDF ) |
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Handout #25 |
Homework #3 Solutions (hardcopy only)* |
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Handout #26 |
Delay-Oriented Technology Mapping Handout (PDF ) |
| Handout #27 |
"Technology Mapping for Low Power," V. Tiwari, P. Ashar and S. Malik, Proceedings of ACM/IEEE Design Automation Conference (1993) (PDF ) |
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Handout #27a |
Errata and Clarifications: Tiwari et al. paper (#27) (TXT ) |
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Handout #28 |
Homework #4 (PDF ) |
| Handout #29 |
"A Procedure for Placement of Standard-Cell VLSI Circuits", A.E. Dunlop and B.W. Kernighan, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Jan. 1985) (PDF ) |
| Handout #30 |
Kernighan-Lin partitioning example (courtesy of Prof. David Pan, UT Austin) (PDF ) |
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Handout #31 |
Midterm CAD Problem (written, SIS) Solutions (hardcopy only)* |
| Handout #32 |
"Retiming Synchronous Circuitry," C.E. Leiserson and J.B. Saxe, Algorithmica (1991), 6:5-35 ( PDF) |
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Handout #33, #33(a-i) |
#33 Final Homework and CAD Project ( PDF ) #33a Introduction to the SIS CAD Package: Technology Mapping ( TXT ) #33b Final CAD Project: Designing a Retiming Tool ( TXT ) #33c Final CAD Project: Correlator Example ( TXT ) #33d Final CAD Project: Alternative Example: More Complex Correlator ( TXT ) #33e Final CAD Project: Input and Output Format Requirements ( TXT ) #33f Important Clarifications (TXT ) #33g Checkpoint Information ( TXT ) #33h Final Report and Submission Information ( TXT ) #33i Final Demo Information ( TXT )
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| Handout #34 |
"An Introduction to High-Level Synthesis", P. Coussy, D.D. Gajski, M. Meredith and A. Takach, IEEE Design and Test of Computers (July/Aug. 2009) (PDF ) |
| Handout #35 |
Resource Sharing Handout (hardcopy only)* |
| Handout #36 |
Scheduling Handout (hardcopy only)* |
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Lecture #12: Slides ( PDF ) |
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| Handout #37 |
Introduction to Asynchronous Design (PDF ) |
| Handout #38 |
Introduction to Hazard-Free Logic Synthesis (PDF ) |
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Handout #39 |
Homework #4 Solutions (hardcopy only)* |