____________________________________________________________________________ CSEE E6861y Handout #34a Prof. Steven Nowick April 9, 2016 ______________________________________________________________________ ______________________________________________________________________ INTRODUCTION TO TECHNOLOGY MAPPING USING SIS ______________________________________________________________________ ______________________________________________________________________ INTRODUCTION This assignment is a short CAD exercise, to introduce you to technology mapping in the SIS CAD flow. Note that for this assignment, you should use SIS. You will simply type commands to the sis command line, produce results, gather statistics, and print out some files. You will be finally running the entire core logic synthesis flow, starting from an initial unoptimized PLA file (2-level) logic, through multi-level optimization (with a script), followed by technology mapping. In particular, you will first run multi-level optimization, using the rugged script (as you tried out in problem #1 of the Midterm CAD Mini-Project). Then, after loading an MCNC cell library, you will run technology mapping, using various modes, to optimize the netlists for area vs. delay. You will be running various versions of the tree-based covering algorithm based on dynamic programming, that we covered in class, and as is presented in the De Micheli reading, ch. 10.3.1. This problem should take you 1-2 hours to complete. ______________________________________________________________________ ______________________________________________________________________ ON-LINE HELP You will be using complex commands, with many options. I strongly suggest that you carefully read the online 'help' for each command, to understand the variety of options, submodes, and switches. Simply type "help " to the SIS command line. E.g. 'help map', 'help set_delay', 'help read_library', 'help write_blif'. ______________________________________________________________________ ______________________________________________________________________ WHAT TO DO: _____________________________________________________________________________ 0. Starting SIS. Create a new directory, and copy two example SIS benchmarks from the benchmark suite: 1. m2 (from indust) 2. ti (from indust) m2 is a moderate example while ti is much larger. Invoke the command "sis" to start your SIS interactive shell. _____________________________________________________________________________ 1. BASIC AREA-ORIENTED RUN: M2 (combined: Multi-Level Optimization and Technology Mapping) DO THE FOLLOWING STEPS: (a) Read in the MCNC 'cell library': read_library mcnc.genlib The file is located under the 'root/sis/sis_lib' folder. It is a text file, so you can take a look at it. Each gate in the library is characterized. This library will be the ultimate target of the technology mapping step. (b) Read in the initial unoptimized 2-level benchmark circuit (PLA format): read_pla Here, 'file_name' is m2. (c) Do multi-level optimization, using the 'rugged' script (as in the Midterm CAD Mini-Project, prob. #1): source script.rugged A script is a text listing, in a fixed order, of a useful sequence of optimization commands. For this part, you will use a famous script, 'rugged script' (script.rugged; see De Micheli, pp. 356-7). It works quite well on a wide variety of examples, and is often used in research papers to report results. (d) Set timing information: For this problem, several defaults are used. We will simply specify the *desired* worst-case delay from inputs-to-outputs to be 40 time units (assuming all inputs are present at time 0): set_delay -R 100 (e) Finally, technology map the m2 circuit from into the loaded MCNC library, under the above timing constraints: map -s -m 0 (NOTE: this is a 'zero', not an 'Oh'). See the online help for 'help map' on details of this mode. This run uses simple modelling assumptions, and is targeted towards AREA OPTIMIZATION. Note the verbose information about the substeps of mapping, including some optimizations. (f) Save the final mapped netlist: Print the resulting mapped netlist to a file, using: 'write_blif -n ' The -n switch indicates to list the actual final library gates in the implementation. WARNING: Do *NOT* type a 'print_stat" command at any point in the middle of the above synthesis run. It may restructure the netlist, and change your final results! _____________________________________________________________________________ 2. BASIC DELAY-ORIENTED RUN: M2 (Multi-Level Optimization and Technology Mapping) Now, repeat steps (b)-(f) for m2 (you do not need to reload the library, so you can skip (a)), with one small modification: for step (e), change the '0' to '1', to get a fully delay-oriented tech map algorithm. _____________________________________________________________________________ 3. MIXED DELAY/AREA-ORIENTED RUN: M2 Finally, repeat #1, steps (b)-(f), but use a 0.5 parameter for step (e) (rather than 0 or 1). This parameter uses a cost function that balances area and delay. _____________________________________________________________________________ 4. ADVANCED DELAY-ORIENTED RUN (part 1): M2 Runs #2 and #3 use a simple model of load delays: each gate contributes a single fixed load to a gate which drives it (i.e. to a gate which feeds it as an input). In this run, we will now use a more expensive and sophisticated load model, which considers the actual loads that each distinct gate provides to its driving input gates. Runtime is longer, but results should be better. (See details in the 'help map' man page.) a. Repeat steps (b)-(d) above. Then, instead of (e), use the command: (e) map -s -n 1 -AFG Then conclude with step (f). _____________________________________________________________________________ 5. ADVANCED DELAY-ORIENTED RUN (part 2): M2 Now, repeat step #4 above, but you are to provide a more aggressive delay constraint (for input-to-output delay), as a target for the algorithm, to force it to work harder to obtain shorter worst-case circuit delays (b)-(c) (repeat from above) (d) set_delay -R 60 (e) (repeat from above: map -s -n 1 -AFG) Then conclude with step (f). _____________________________________________________________________________ 6. MULTI-LEVEL OPTIMIZATION AND TECHNOLOGY MAPPING: TI Now, repeat steps #1-5 above, but for the 'ti' example. Make the following small changes: when repeating #1-4 on this new example, for step (d), use: set_delay -R 60 when repeating step #5 on this new example, for step (d), use: set_delay -R 40 _____________________________________________________________________________ WHAT TO HAND IN (a) TABLE OF RESULTS: "M2" EXAMPLE Hand in a table of results for m2, summarizing the results of steps #1-5 above. In particular, for each of the 5 distinct runs (clearly labelled), indicate: - final total area - final total delay These results are visible during each run, as the final 'total gate area' and 'maximum arrival time' entries in the interactive display after running step (e). (Be sure not to use the initial listings, before optimization; just use the final listings towards the bottom of the interactive output.) (b) TABLE OF RESULTS: "TI" EXAMPLE Generate a similar table for your 5 runs on benchmark example 'ti' (step #6 above). _____________________________________________________________________________ _____________________________________________________________________________