STEVEN M. NOWICK

Office:

                Department of Computer Science
                Columbia University
                Computer Science Building; Mail Code: 0401
                1214 Amsterdam Avenue
                New York, NY 10027

Phone: (212) 939-7056
FAX: (646) 775-6023

E-mail: nowick AT cs DOT columbia DOT edu

Short Bio:

I am a Professor Emeritus of Computer Science (and, by courtesy, Electrical Engineering) at Columbia University, and was a co-founder and chair of the interdisciplinary Computer Engineering Program, joint between CS and EE departments. I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976. I retired from Columbia in 2019.

My main research interests are: the design and optimization of asynchronous and mixed-timing digital systems (globally-asynchronous locally-synchronous [GALS]); scalable high-performance and low-power on-chip networks for parallel processors and embedded systems; computer-aided digital design and optimization (CAD); fault tolerance and reliability; and ultra-low-energy digital systems.

I am an IEEE Fellow (2009), and recipient of an Alfred P. Sloan Research Fellowship (1995), and NSF CAREER (1995) and RIA (1993) Awards, and am a Senior Member of the ACM. I received Best Paper Awards at the IEEE International Conference on Computer Design (1991, 2012) and the IEEE Async Symposium (2000). I co-founded the IEEE "Async" Symposia series (1994), now in its 31st year, and was its Program Committee Chair (1994, 1999) and General Chair (2005). I was Program Chair of the ACM/IEEE International Workshop on Logic and Synthesis (IWLS, 2005), and Program Track/Subcommittee Chair at DAC, DATE and ICCD conferences. I served on the editorial boards of several leading journals: IEEE Design & Test Magazine, IEEE Transactions on Computer-Aided Design, IEEE Transactions on VLSI Systems, and ACM Journal on Emerging Technologies in Computer Systems. I also served as a guest editor for a special issue of the Proceedings of the IEEE (Feb. 1999).

I was the selection committee chair of ACM/SIGDA's Outstanding Dissertation in EDA (Electronic Design Automation) Award, a selection committee member of the ACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation, a jury member of the ACM India Doctoral Dissertation Award, and a member of the Best Paper Award committees for ACM/IEEE DAC and ICCAD conferences. I am also a recipient of the Columbia Engineering School Alumni Distinguished Faculty Teaching Award (2011). I hold 13 issued US patents.

My industrial collaboration and technology transfer, of our group's asynchronous digital designs and methodologies, include: (i) to NASA Goddard Space Center (Greenbelt, MD), for joint design of an experimental laser space measurement circuit for space applications, using our asynchronous "burst-mode" controllers and Minimalist CAD tool; (ii) to IBM T.J. Watson Research, for joint design of a mixed async-sync experimental low-power chip for an FIR filter for disk drive reads, using our "high-capacity" asynchronous pipelines, which out-performed the best comparable IBM synchronous commercial design; and (iii) to AMD Corporation, implementing our low-latency and low-energy asynchronous network-on-chip switch for multicore systems, using advanced 14nm FinFET technology, which significantly outperformed one of their recent commercial synchronous designs. (See "Research Summary" and CV below for details.)

Data Science Institute: Chair/Founder of Research Center

I am also the founder and original chair of a new Columbia University research center, Computing Systems for Data-Driven Science (2018-2019), which has over 45 faculty members. The center is part of Columbia's Data Science Institute (DSI). It was formerly a working group, "Frontiers in Computing Systems," which I also founded and chaired (2016-2018). Its focus is on the design and application of large-scale computing systems to break through barriers in processing vast scientific data sets.

The center brings together diverse researchers across Columbia, from 5 schools and institutes, coming from 15 departments, in three areas: (i) computing systems (incl. hardware design, parallel computer architecture, distributed and cloud computing, software programming environments, databases, and emerging computational paradigms); (ii) data science, machine learning and AI; and (iii) computational application areas in science, engineering and medicine (e.g. ocean and climate science, astronomy, materials science, civil engineering, chemistry, physics, biomedical informatics, and computational genomics). Its goal is to foster new and exciting cross-disciplinary collaborations and research projects between these areas.

See initial news story on our working group (July 2016), as well as a summary of our inaugural symposium (story) (March 2017). The event had over 150 attendees.

Our DSI center also hosted the 2019 New York Scientific Data Summit (NYSDS-19), which we co-organized with Brookhaven National Laboratory's Computational Science Initiative (June 12-14), in Davis Auditorium on Columbia's Morningside Campus. The event is the leading regional symposium focusing on large-scale computational problems in science/medicine/engineering, computing systems, and data analytics. See a news story on the event. For agenda and details, see the NYSDS-19 web site.

My Retirement from Columbia University (July 2019)

CS Dept. Article on My 2019 Retirement + September 2019 Retirement Party: (HTML) (PDF)

Research Overview

Short Profile of My Research (PDF): (click here)

Recent Professional Highlights (2008-present [2018]) (PDF): (click here)

Detailed Research Summary (July 2018) (PDF): (click here) (covers my main research areas, recent papers, technology transfer, grants)

Bio's and CV's:

Short Bio (journal style)

Extended Bio

Complete CV (July 2021)

Recent News...:

2017:

Congratulations to PhD student Kshitij Bhardwaj for his accepted ACM/IEEE NOCS-17 paper on supporting multicast communication in asynchronous on-chip interconnection networks! (Best Paper Nomination)

Prof. Nowick launches the inaugural Frontiers in Computing Systems symposium, in Davis Auditorium, on March 24, 2017, with 150 attendees. The symposium includes a diverse lineup of world-leading speakers and panelists, in computer systems and applications areas, including keynote Ruchir Puri (chief architect, IBM "Watson" system), and welcome by G. Michael Purdy (executive vice president of research, Columbia University); see recent news story.

Congratulations to PhD student Weiwei Jiang for his accepted IEEE Async-17 paper on a high-performance asynchronous multi-resource arbiter design!

Congratulations to PhD student Weiwei Jiang for his accepted ACM/IEEE DATE-17 industrial track paper, in collaboration with AMD Research and University of Ferrara, based on his recent AMD internship! The paper describes the implementation of our asynchronous network-on-chip [NoC] in advanced 14nm industrial FinFET technology, and a direct experimental comparison to a recent commercial AMD synchronous NoC, with dominating results: 55% less area, 28% lower latency, and 58% (/88%) savings in active (/idle) power.

2016:

Prof. Nowick launches new working group, Frontiers in Computing Systems, which is part of the Columbia Data Science Institute (DSI) (expected to become a full center within the next year). There are currently 35 members. The working group aims to explore the design, analysis and application of extreme-scale computing systems for processing data, in the most general sense. It brings together diverse researchers at Columbia in computing systems (hardware, parallel architecture, distributed computing, cloud computing, databases -- as well as neuroscience) and application areas (oceanography, climate science, materials science, civil engineering, astronomy, physics, biomedical informatics, computational genomics, and neuroscience). See recent news story.

Congratulations to PhD student Kshitij Bhardwaj for obtaining an internship at Intel (Hillsboro) from July to October, to work on energy-efficient networks-on-chip!

Congratulations to PhD student Kshitij Bhardwaj for his accepted ACM/IEEE DAC-16 paper on efficient multicast communication in asynchronous networks-on-chip, using a mesh-of-trees (MoT) topology!

Professor Nowick was invited to 4 Program Committees in 2016 (DATE, Async, NOCS, and IWLS) and served as associate editor of 3 journals (IEEE Design and Test, IEEE Transactions on VLSI Systems, ACM Journal on Emerging Technologies in Computing Systems).

2015:

Professor Nowick receives an NSF grant to develop asynchronous on-chip interconnection networks (June 2015) (click here).

Prof. Nowick participates in 2 national study groups (see recent CS department story click here).

Professor Nowick is the keynote speaker at the 17th ACM/IEEE System Level Interconnection Prediction (SLIP) Workshop in San Francisco (June 2015). (click here).

Congratulations to PhD student/former visiting intern Gabriele Miorandi (U. of Ferrara) who, with Prof. Nowick and his advisor Prof. Davide Bertozzi (U. of Ferrara), is a Best Paper Finalist in the 21st IEEE International Symposium on Asynchronous Circuits and Systems (Async), for their paper "Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters" (May 2015).

Congratulations to PhD student Kshitij Bhardwaj for obtaining a summer internship at Cadence Design Systems, and to PhD student Weiwei Jiang for obtaining a summer internship at AMD Research!

Congratulations to PhD students Weiwei Jiang and Kshitij Bhardwaj and former MS student Geoffray Lacourba, for their accepted ACM/IEEE DAC-15 paper on an asynchronous 2D-mesh network-on-chip with early arbitration resolution!

Professor Nowick is an invited participant in the NSF Workshop on Ultra-Low Latency Wireless Networks (March 2015), a national study group to explore the future of wireless communication for both macro-networks and networks-on-chip (click here).

Professor Nowick is sub-committee co-chair of the ACM/IEEE Design, Automation and Test in Europe Conference Program Committee (2015), in the network-on-chip area.

Professor Nowick has joined the editorial boards of IEEE Design & Test Magazine and IEEE Transactions on VLSI Systems, each for a two-year term (January 2015).

Professor Nowick was invited to 5 Program Committees in 2015: DATE, Async, NOCS, IWLS and INA-OCMC.

2014:

Welcome to new PhD student Kunal Mahajan, who comes from the UPenn Computer Engineering program! (Fall 2014)

Professor Nowick is an invited participant in the NSF/DARPA/DOE/NASA Workshop on System-on-Chip Design for High-Performance Computing ("SoC for HPC") (August 2014), a national study group on the future of designing cost-effective high-performance parallel computers for both big data and consumer applications (click here).

Congratulations to former PhD student Michael Theobald, who is part of the D.E. Shaw Research team winning the 2014 ACM Gordon Bell Prize for best performance of a high-performance computing application, for the Anton 2 Parallel Processor, a special-purpose supercomputer for molecular dynamics simulation!

Professor Nowick is a selection committee member for the William J. McCalla Best Paper Award for the ACM/IEEE International Conference on Computer-Aided Design (2014).

Professor Nowick is a selection committee member for the ACM/IEEE "A. Richard Newton Technical Impact Award in Electronic Design Automation" (2014-2015). This annual award honors an outstanding publication with the greatest long-term technical impact in the field of electronic design automation.

Professor Nowick was invited to 5 Program Committees in 2014: DATE, Async, NOCS, IWLS and INA-OCMC.

2013:

Professor Nowick gives an invited talk at AMD Research (Boxborough, MA) on his research on asynchronous and GALS networks-on-chip, broadcast to multiple AMD sites (November 2013).

Congratulations to PhD student Christos Vezyrtzis, who successfully defends his thesis and begins a job as a Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY (May 2013)!

Professor Nowick is subcommittee chair of the 50th ACM/IEEE Design Automation Conference Program Committee (2011-2013), in the logic- and high-level synthesis and FPGA area. DAC is the leading international conference in design and CAD for electronic systems.

Professor Nowick is the selection committee chair for the ACM/SIGDA "Outstanding PhD Dissertation in EDA Award" (2012-2013). This international award is provided by the Association of Computing Machinery (ACM), the leading computer science professional society, through its Special Interest Group in Electronic Design Automation (SIGDA), for the best dissertation award in this research area.

Professor Nowick gives invited talk at the Computer Engineering Eminent Research Seminar series sponsored by the Texas A&M University ECE Department (April 2013).

Congratulations to PhD student Alberto Ghiribaldi (U. of Ferrara) who, with Prof. Nowick and his advisor Prof. Davide Bertozzi (U. of Ferrara), is a Best Paper Finalist in the ACM/IEEE Design, Automation and Test in Europe (DATE) Conference, for their paper "A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-Effective GALS Multicore Systems" (March 2013).

Professor Nowick was invited to 6 Program Committees in 2013: DAC, DATE, Async, NOCS, IWLS and INA-OCMC.

2012:

PhD student Christos Vezyrtzis, with co-advisors Profs. Nowick (CS) and Tsividis (EE), wins Best Paper Award in the Logic and Circuit Design track of the 30th IEEE International Conference on Computer Design (ICCD), for their paper "Designing Pipelined Delay Lines with Dynamically-Adaptive Granularity for Low-Energy Applications" (October 2012).

Professor Nowick receives an NSF grant to explore and develop dynamically-adaptable on-chip networks (click here for Engineering School profile) (June 2012).

Research Slides:

Overview:

"Recent Advances in Designing Clockless Digital Systems" (click here): A short introduction to asynchronous design, recent industrial developments, and overview of my research.

Networks-on-Chip:

"A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors" (click here): Integrating heterogeneous clocked processors and memories in a shared-memory parallel architecture using a high-performance low-power asynchronous interconnection network.

High-Performance Pipelines:

"Introduction to Mousetrap Asynchronous Pipelines" (click here): Designing high-speed asynchronous pipelines.

Mixed-Timing Interfaces:

"Robust Interfaces for Mixed-Timing Systems" (click here): Designing robust and low-latency interface circuits for mixed-clock and mixed asynchronous/synchronous systems.

Overview Papers:

D. Bertozzi, G. Miorandi, A. Ghiribaldi, W. Burleson, G. Sadowski, K. Bhardwaj, W. Jiang and S.M. Nowick, "Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems," (click here) IEEE Micro Magazine, vol. 41:1, pp. 69-81, Jan./Feb. 2021).
Provides an introduction to our complete methodology for design low-latency and power-efficient asynchronous on-chip networks. The approach includes: a network-on-chip (NoC) microarchitecture and design, a complete CAD tool flow harnessing synchronous commercial EDA tools, detailed comparisons with synchronous designs in identical technology, and re-implementation at AMD Research (Boxborough, MA) in advanced 14nm FinFET commercial technology. We also provide direct normalized comparisons, for the first time, with some other influential asynchronous NoC designs.
Our asynchronous design is largely dominating, in comparison to some leading synchronous designs in both academia and industry, in most cost metrics: area, power and performance.
In comparison to an ultra-low power synchronous NoC using state-of-art clock gating, our async NoC, projected to a full HD video playback application for high-end mobile devices, exhibits up to 45% power improvements and 37% latency savings.
Moreover, we were invited to collaborate by AMD, and together we reimplemented one of their recent commercial synchronous NoCs in identical advanced (14nm FinFET) technology. Results confirm substantial benefits: 55% lower area, 28% lower latency, and reductions of 88% idle and 58% active power. This is the first apples-to-apples comparison of asynchronous to commercial synchronous general-purpose NoCs in advanced technology.

S.M. Nowick and M. Singh, "Asynchronous Design -- Part 1: Overview and Recent Advances," (click here) IEEE Design and Test, vol. 32:3, pp. 5-18, May/June 2015).

S.M. Nowick and M. Singh, "Asynchronous Design -- Part 2: Systems and Methodologies," (click here) IEEE Design and Test, vol. 32:3, pp. 19-28, May/June 2015).
Provides a broad and modern overview of state-of-the-art of the field of asynchronous design. Includes a short history of asynchronous design, as well as a technical introduction to handshaking protocols and data encoding. Also, covers recent industrial successes in mainstream technologies (IBM, Intel, Philips Semiconductors, etc.), as well as recent application to emerging areas (neuromorphic computers, flexible electronics, quantum cellular automata, continuous-time DSPs, ultra-low voltage design, extreme environments). Highlights several application areas in depth, with a wide range of cited publications: GALS systems, networks-on-chip, computer architecture, testing and design-for-testability, and CAD tool development.

S.M. Nowick and M. Singh, "High-Performance Asynchronous Pipelines: an Overview," (click here) IEEE Design and Test of Computers, special issue on asynchronous design, vol. 28:5, pp. 8-22 (September/October 2011).
Provides a good basic introduction to asynchronous pipelines. Includes basic background on handshaking protocols, industrial developments, as well as a detailed technical introduction to several leading high-performance pipelines, and their use at Intel, Achronix Semiconductor, and other companies.

Selected Research Papers + Slides:

W. Jiang, D. Bertozzi, G. Miorandi, S.M. Nowick, W. Burleson and G. Sadowski, "An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart," (click here) ACM/IEEE Design, Automation and Test in Europe Conference (DATE-17), Lausanne, Switzerland (March 2017).
In collaboration with AMD Research, migrating our asynchronous network-on-chip into advanced 14nm FinFET industrial technology, with a direct head-on-head comparison with an AMD commercial network-on-chip (NoC). This is the first "apples-to-apples" comparison of an asynchronous NoC in advanced technology to a commercial chip. Our asynchronous network-on-chip exhibited dominating results: 55% less circuit area, 28% lower latency, and 58% (/88%) savings in active (/idle) power. For slides, click here.

G. Miorandi, M. Balboni, S.M. Nowick and D. Bertozzi, "Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow," (click here) IEEE International Symposium on Asynchronous Circuits and Systems (Async-17), San Diego, CA (May 2017).
An automated tool flow for asynchronous networks-on-chip using synchronous commercial CAD tools (joint with University of Ferrara, Italy).

Recent Web Articles (grants and tool releases):

Steven Nowick Invited To Present Work on Asynchronous On-Chip Networks at Two National Study Groups" -- CS department news story (July 2015)

Prof. Nowick Developing New Dynamically-Adaptable On-Chip Networks" -- Engineering School profile on my NSF grant (June 2012)

Profs. Nowick and Tsividis Developing Ultra-Low Energy Continuous-Time Signal Processors" -- Engineering School profile on my medium-scale NSF grant (May 2010)

"Columbia Engineering News": "Nowick Developing New Desktop Supercomputer" -- story on my medium-scale NSF team grant, joint with University of Maryland (Summer 2008)

"EE Times (Europe)" -- article on our "CaSCADE" Asynchronous CAD Tool Release (December 2007)

"Columbia Engineering News": "New Information Technology" -- cover story on my two Medium-Scale NSF ITR Awards (Fall 2000)

Asynchronous Design in the News...:

"Faster Chips That March to Their Own Improvised Beat (click here): Article in the New York Times, Circuits Section (August 22, 2002). Includes an interview with Professor Nowick.

"It's Time for Clockless Chips (click here): Cover story in Technology Review Magazine (based in MIT), October 2001, vol. 104:8 (pp. 36-41). Includes an interview with Professor Nowick.

"ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor" (from ARM Ltd. web page, Oct. 2004)

Clockless Computing: Coordinating Billions of Transistors (Washington University 150th Anniversary Symposium) (click here): Washington University Symposium, St. Louis, Missouri (March 26, 2004). Includes an invited presentation by Professor Nowick.

"Designers Look to Take Computer Chips Off the Clock" (click here): Article in Newsfactor Network (September 18, 2001) on goals and recent achievements of asynchronous design.

"Computing Pioneer Challenges the Clock" (click here) : Article in the New York Times (March 5, 2001) on Ivan Sutherland's group at Sun Microsystems Lab, and their recent advances in developing high-speed asynchronous circuits.

"Old Tricks for New Chips" (click here): Article in The Economist (April 19, 2001) on the promise of asynchronous circuits.

Research Team:

Back row (left to right): Yu Chen, Kshitij Bhardwaj, Steve Nowick, Christos Vezyrtzis, Weiwei Jiang

Front row (left to right): Adil Sadik, George Faldamis

Former Post-Doctoral Research Scientists:

Gennette Gill (D.E. Shaw Research Laboratory, New York, NY)

Former PhD Students:

Kshitij Bhardwaj (first position: Post-Doctoral Research Fellow, Harvard University [Computer Architecture and VLSI group, EE/CS Depts., leads: Profs. David Brooks/Gu-Yeon Wei]; current position: Computer Scientist, Lawrence Livermore National Laboratory [Parallel Systems Group, Center for Applied and Scientific Computing])

Weiwei Jiang (first position: Senior R&D Engineer, Synopsys Corporation, Mountain View, CA [FPGA Synthesis Team, Verification Group]; current position: Architecture and Design Engineer, Accelerator ASIC, Google, Sunnyvale, CA)

Christos Vezyrtzis (first position: Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY; current position: IC Design Expert, Bitmain, San Jose, CA)

Melinda Agyekum (Program Manager, Enterprise Storage Backend, Google, New York, NY)

Peggy McGee (Senior R&D Engineer, Power Compiler group, Synopsys Corporation, Sunnyvale, CA)

Cheoljoo Jeong (Senior Design Engineer, Cadence Design Systems, Sunnyvale, CA)

Cheng-Hong Li (became student of Prof. Luca Carloni, now at Google)

Tiberiu Chelcea (first position: Postdoctoral Fellow, CS Department, CMU [Prof. Seth Goldstein's group])

Michael Theobald ( first position: Postdoctoral Fellow, CS Department, CMU [Prof. Ed Clarke's group]; current position: Researcher, D.E. Shaw Research Laboratory, New York, NY)

Montek Singh (Associate Professor, CS Department, University of North Carolina - Chapel Hill)

Robert Fuhrer ( first position: IBM T.J. Watson Research Center, Yorktown, NY; current position: Software Engineer, Google, New York, NY)

Kunal Mahajan (transferred to Vishal Misra and Dan Rubenstein)

Yu Chen (EE, became student of Prof. Yannis Tsividis)

Former Collaborating PhD Students:

Gabriele Miorandi (University of Ferrara [D. Bertozzi group])

Alberto Ghiribaldi (University of Ferrara [D. Bertozzi group])

Former MS Students: (partial list)

Sumedh Attarde (Server Design group, Intel Corporation, Santa Clara, CA)

Clementine Barbet (Comp Eng)

Marco Cannizzaro (MS co-advisor; from Politecnico di Torino, Italy)

Walter Dearing

Georgios (George) Faldamis (Cavium, Inc.)

Michael Horak [U. of Maryland, co-chair of MS thesis committee] (Advanced Simulation Technology, Inc.)

Roopa Kakarlapudi

Kiran Kumar Mada

Geoffray Lacourba (ARM Ltd., France)

Amitava Mitra (Intel India)

Ashwath Narasimhan

Harsh Parekh

Ankit Pradhan

Adil Sadik

David Solimano

Srikanth Viswanathan

Wei Wei (CDM verification engineer, CPU design and verification team, Apple Corporation)

Former Undergraduate Project Students: (partial list)

Steven Callender (Intel Hillsboro; formerly UC Berkeley, PhD Student)

Matthew Carlberg

David Hughes

William Liu

William McLaughlin

Charles O'Donnell (MIT, PhD Student)

Teaching:

Fall 16: CSEE W4823 Advanced Logic Design

Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs4823

Spring 16: CSEE E6861 Computer-Aided Design of Digital Systems

Course Advertisement: (click here)

Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs6861

Office Hours:

Fall-16: Monday 4:30-5:30pm, Thursday 4:00-5:00pm

Room 508, Computer Science Building

phone: (212) 939-7056

ASYNCHRONOUS CAD TOOL PACKAGES

"The CaSCADE Package" is our new asynchronous design environment, including six different tools and libraries. The acronym "CaSCADE" = "Columbia University and University of Southern California Asynchronous Design Environment". It was developed under NSF ITR Award No. NSF-CCR-0086036, with support from additional grants (see CaSCADE web pages for details). This set of asynchronous CAD tools is available for free download for use with Linux platforms.

Three of the tools in the CaSCADE package were developed and maintained by our Columbia asynchronous research group: (a) "MINIMALIST" for asynchronous controllers; (b) the "ATN_OPT Toolset" for robust asynchronous threshold networks; and (c) the "DES (Discrete Event System) Analyzer" for performance analysis and timing verification of concurrent systems.

(a) The MINIMALIST CAD Package, release v2.0: "MINIMALIST" is a comprehensive CAD package for the automated synthesis and optimization of asynchronous controllers. It includes a Verilog back-end, multi-level logic optimizer, decomposition tool for large specifications, verifier, online help and graphical interfaces. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download Minimalist (including extensive tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(b) The ATN_OPT Toolset, release v0.1: The "ATN_OPT" Toolset is a comprehensive CAD package for the automated synthesis and optimization of robust dual-rail asynchronous threshold networks. It supports circuit descriptions in several common formats (Verilog/VHDL/BLIF), and supports cell libraries defined in GENLIB format. It allows several user-specified optimization targets: area, delay, power, and delay-area tradeoffs. It also includes a user shell. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download ATN_OPT (including tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(c) The DES (Discrete Event System) Analyzer, release v0.1: The "DES Analyzer" is a comprehensive CAD package for performance analysis and timing verification of concurrent digital systems. It includes two tools: (i) "DES-PERF" which uses user-supplied stochastic information to compute asymptotic system performance, and (ii) "DES-TSE", which uses user-supplied min/max delay bounds on individual events to compute the global min/max "time-separation-of events" between any two pairs of events. The DES-TSE tool is especially useful in determining which orderings of concurrent events are impossible in the actual global evolution of a concurrent system (going from startup to steady-state) -- potentially useful for optimizing the system -- as well as providing min/max bounds on the system's cycle time (and hence min/max bounds on system throughput). The tool accepts system specifications in the form of a restricted classof Petri net (i.e. "marked graph"), and includes several user options, graphical interfaces, and detailed output reports. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download the DES Analyzer (and tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)