Department of Computer Science
Office:
Phone: (212) 939-7056
FAX: (646) 775-6023
E-mail: nowick AT cs DOT columbia DOT edu
I am a Professor of Computer Science (and, by courtesy, Electrical Engineering). I am a co-founder and former chair of the Computer Engineering Program at Columbia University. I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976. My main research interests are: design and optimization of asynchronous and mixed-timing digital systems (globally-asynchronous locally-synchronous [GALS]); scalable high-performance and low-power on-chip networks for parallel processors and embedded systems; computer-aided digital design and optimization (CAD); fault tolerance and reliability; and ultra-low-energy digital systems.
I am the founder and chair of a new university research center, Computing Systems for Data-Driven Science, which is part of the Columbia Data Science Institute (DSI), which has over 40 faculty members. (It was formerly a working group, "Frontiers in Computing Systems.") Its focus is on exploring the design and application of large-scale computing systems to break through current barriers in processing and analyzing vast data sets. The brings together diverse researchers at Columbia in three areas: (i) computing systems (hardware, parallel computer architecture, distributed and cloud computing, software programming environments, databases, quantum computing, emerging paradigms); (ii) data science and machine learning; and (iii) large-scale computational application areas in science, engineering and medicine (e.g. ocean/climate science, astrophysics, materials science, civil engineering, physics, biomedical informatics, and computational genomics). The center fosters new projects and initiatives between these areas. See initial news story (July 2016), as well as a summary of our recent inaugural symposium ( story and agenda) (March 2017).
Short Profile of My Research (PDF): (click here)
Recent Professional Highlights (2008-present [2018]) (PDF): (click here)
Detailed Research Summary (July 2018) (PDF): (click here) (covers my main research areas, recent papers, technology transfer, grants)
Bio's and CV's:
Recent News...:
2017:
2016:
2015:
2014:
2013:
2012:
Research Slides:
Overview:
Networks-on-Chip:
High-Performance Pipelines:
Mixed-Timing Interfaces:
Overview Papers:
Provides a broad and modern overview of state-of-the-art of the field of asynchronous design. Includes a short history of asynchronous design, as well as a technical introduction to handshaking protocols and data encoding. Also, covers recent industrial successes in mainstream technologies (IBM, Intel, Philips Semiconductors, etc.), as well as recent application to emerging areas (neuromorphic computers, flexible electronics, quantum cellular automata, continuous-time DSPs, ultra-low voltage design, extreme environments). Highlights several application areas in depth, with a wide range of cited publications: GALS systems, networks-on-chip, computer architecture, testing and design-for-testability, and CAD tool development.
Provides a good basic introduction to asynchronous pipelines. Includes basic background on handshaking protocols, industrial developments, as well as a detailed technical introduction to several leading high-performance pipelines, and their use at Intel, Achronix Semiconductor, and other companies.
Provides a basic overview of asynchronous design (less up-to-date but more comprehensive than above paper).
Selected Research Papers + Slides:
In collaboration with AMD Research, migrating our asynchronous network-on-chip into advanced 14nm FinFET industrial technology, with a direct head-on-head comparison with an AMD commercial network-on-chip (NoC). This is the first "apples-to-apples" comparison of an asynchronous NoC in advanced technology to a commercial chip. Our asynchronous network-on-chip exhibited dominating results: 55% less circuit area, 28% lower latency, and 58% (/88%) savings in active (/idle) power. For slides, click here.
An automated tool flow for asynchronous networks-on-chip using synchronous commercial CAD tools (joint with University of Ferrara, Italy).
Recent Web Articles (grants and tool releases):
Steven Nowick Invited To Present Work on Asynchronous On-Chip Networks at Two National Study Groups" -- CS department news story (July 2015)
Prof. Nowick Developing New Dynamically-Adaptable On-Chip Networks" -- Engineering School profile on my NSF grant (June 2012)
Profs. Nowick and Tsividis Developing Ultra-Low Energy Continuous-Time Signal Processors" -- Engineering School profile on my medium-scale NSF grant (May 2010)
"Columbia Engineering News": "Nowick Developing New Desktop Supercomputer" -- story on my medium-scale NSF team grant, joint with University of Maryland (Summer 2008)
"EE Times (Europe)" -- article on our "CaSCADE" Asynchronous CAD Tool Release (December 2007)
"Columbia Engineering News": "New Information Technology" -- cover story on my two Medium-Scale NSF ITR Awards (Fall 2000)
Asynchronous Design in the News...:
Research Team:
Back row (left to right): Yu Chen, Kshitij Bhardwaj, Steve Nowick, Christos Vezyrtzis, Weiwei Jiang
Front row (left to right): Adil Sadik, George Faldamis
Current PhD Students:
Weiwei Jiang
Former Post-Doctoral Research Scientists:
Gennette Gill (D.E. Shaw Research Laboratory, New York, NY)
Former PhD Students:
Christos Vezyrtzis (Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY)
Melinda Agyekum (Program Manager, Enterprise Storage Backend, Google, New York, NY)
Peggy McGee (senior R&D engineer, Power Compiler group, Synopsys Corporation, Sunnyvale, CA)
Cheoljoo Jeong (staff R&D engineer, Verification group, Synopsys Corporation, Mountain View, CA; formerly senior design engineer, Cadence Design Systems, Sunnyvale, CA)
Cheng-Hong Li (became student of Prof. Luca Carloni, now NEC Research Laboratories)
Tiberiu Chelcea (formerly Postdoctoral Fellow, CS Department, CMU)
Michael Theobald (Researcher, D.E. Shaw Research Laboratory, New York, NY; formerly Postdoctoral Fellow, CS Department, CMU)
Montek Singh (Associate Professor, CS Department, University of North Carolina - Chapel Hill)
Robert Fuhrer (IBM T.J. Watson Research Center, Yorktown, NY )
Kunal Mahajan (transferred to Vishal Misra and Dan Rubenstein)
Yu Chen (EE, became student of Prof. Yannis Tsividis)
Former Collaborating PhD Students:
Gabriele Miorandi (University of Ferrara [D. Bertozzi group])
Alberto Ghiribaldi (University of Ferrara [D. Bertozzi group])
Former MS Students: (partial list)
Sumedh Attarde (Server Design group, Intel Corporation, Santa Clara, CA)
Clementine Barbet (Comp Eng)
Marco Cannizzaro (MS co-advisor; from Politecnico di Torino, Italy)
Walter Dearing
Georgios (George) Faldamis (Cavium, Inc.)
Michael Horak [U. of Maryland, co-chair of MS thesis committee] (Advanced Simulation Technology, Inc.)
Roopa Kakarlapudi
Kiran Kumar Mada
Geoffray Lacourba (ARM Ltd., France)
Amitava Mitra (Intel India)
Ashwath Narasimhan
Harsh Parekh
Ankit Pradhan
Adil Sadik
David Solimano
Srikanth Viswanathan
Wei Wei (CDM verification engineer, CPU design and verification team, Apple Corporation)
Former Undergraduate Project Students: (partial list)
Steven Callender (UC Berkeley, PhD Student)
Matthew Carlberg
David Hughes
William Liu
William McLaughlin
Charles O'Donnell (MIT, PhD Student)
Spring 16: CSEE E6861 Computer-Aided Design of Digital Systems
Course Advertisement: (click here)
Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs6861
Fall 15: CSEE W4823 Advanced Logic Design
Course Advertisement: (click here)
Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs4823
Spring-16: Tuesday 3:00-4:00pm, Wednesday 2:30-3:30pm
Room 508, Computer Science Building
phone: (212) 939-7056
"The CaSCADE Package" is our new asynchronous design environment, including six different tools and libraries. The acronym "CaSCADE" = "Columbia University and University of Southern California Asynchronous Design Environment". It was developed under NSF ITR Award No. NSF-CCR-0086036, with support from additional grants (see CaSCADE web pages for details). This set of asynchronous CAD tools is available for free download for use with Linux platforms.
Three of the tools in the CaSCADE package were developed and maintained by our Columbia asynchronous research group: (a) "MINIMALIST" for asynchronous controllers; (b) the "ATN_OPT Toolset" for robust asynchronous threshold networks; and (c) the "DES (Discrete Event System) Analyzer" for performance analysis and timing verification of concurrent systems.
(a) The MINIMALIST CAD Package, release v2.0: "MINIMALIST" is a comprehensive CAD package for the automated synthesis and optimization of asynchronous controllers. It includes a Verilog back-end, multi-level logic optimizer, decomposition tool for large specifications, verifier, online help and graphical interfaces. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download Minimalist (including extensive tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)
(b) The ATN_OPT Toolset, release v0.1: The "ATN_OPT" Toolset is a comprehensive CAD package for the automated synthesis and optimization of robust dual-rail asynchronous threshold networks. It supports circuit descriptions in several common formats (Verilog/VHDL/BLIF), and supports cell libraries defined in GENLIB format. It allows several user-specified optimization targets: area, delay, power, and delay-area tradeoffs. It also includes a user shell. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download ATN_OPT (including tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)
(c) The DES (Discrete Event System) Analyzer, release v0.1: The "DES Analyzer" is a comprehensive CAD package for performance analysis and timing verification of concurrent digital systems. It includes two tools: (i) "DES-PERF" which uses user-supplied stochastic information to compute asymptotic system performance, and (ii) "DES-TSE", which uses user-supplied min/max delay bounds on individual events to compute the global min/max "time-separation-of events" between any two pairs of events. The DES-TSE tool is especially useful in determining which orderings of concurrent events are impossible in the actual global evolution of a concurrent system (going from startup to steady-state) -- potentially useful for optimizing the system -- as well as providing min/max bounds on the system's cycle time (and hence min/max bounds on system throughput). The tool accepts system specifications in the form of a restricted classof Petri net (i.e. "marked graph"), and includes several user options, graphical interfaces, and detailed output reports. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download the DES Analyzer (and tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)