Office:

2017:

• Congratulations to PhD student Kshitij Bhardwaj for his accepted ACM/IEEE NOCS-17 paper on supporting multicast communication in asynchronous on-chip interconnection networks! (Best Paper Nomination)

• Prof. Nowick launches the inaugural Frontiers in Computing Systems symposium, in Davis Auditorium, on March 24, 2017, with 150 attendees. The symposium includes a diverse lineup of world-leading speakers and panelists, in computer systems and applications areas, including keynote Ruchir Puri (chief architect, IBM "Watson" system), and welcome by G. Michael Purdy (executive vice president of research, Columbia University); see recent news story.

• Congratulations to PhD student Weiwei Jiang for his accepted IEEE Async-17 paper on a high-performance asynchronous multi-resource arbiter design!

• Congratulations to PhD student Weiwei Jiang for his accepted ACM/IEEE DATE-17 industrial track paper, in collaboration with AMD Research and University of Ferrara, based on his recent AMD internship! The paper describes the implementation of our asynchronous network-on-chip [NoC] in advanced 14nm industrial FinFET technology, and a direct experimental comparison to a recent commercial AMD synchronous NoC, with dominating results: 55% less area, 28% lower latency, and 58% (/88%) savings in active (/idle) power.

2016:

• Prof. Nowick launches new working group, Frontiers in Computing Systems, which is part of the Columbia Data Science Institute (DSI) (expected to become a full center within the next year). There are currently 35 members. The working group aims to explore the design, analysis and application of extreme-scale computing systems for processing data, in the most general sense. It brings together diverse researchers at Columbia in computing systems (hardware, parallel architecture, distributed computing, cloud computing, databases -- as well as neuroscience) and application areas (oceanography, climate science, materials science, civil engineering, astronomy, physics, biomedical informatics, computational genomics, and neuroscience). See recent news story.

• Congratulations to PhD student Kshitij Bhardwaj for obtaining an internship at Intel (Hillsboro) from July to October, to work on energy-efficient networks-on-chip!

• Congratulations to PhD student Kshitij Bhardwaj for his accepted ACM/IEEE DAC-16 paper on efficient multicast communication in asynchronous networks-on-chip, using a mesh-of-trees (MoT) topology!

• Professor Nowick was invited to 4 Program Committees in 2016 (DATE, Async, NOCS, and IWLS) and served as associate editor of 3 journals (IEEE Design and Test, IEEE Transactions on VLSI Systems, ACM Journal on Emerging Technologies in Computing Systems).

2015:

• Professor Nowick receives an NSF grant to develop asynchronous on-chip interconnection networks (June 2015) (click here).

• Prof. Nowick participates in 2 national study groups (see recent CS department story click here).

• Professor Nowick is the keynote speaker at the 17th ACM/IEEE System Level Interconnection Prediction (SLIP) Workshop in San Francisco (June 2015). (click here).

• Congratulations to PhD student/former visiting intern Gabriele Miorandi (U. of Ferrara) who, with Prof. Nowick and his advisor Prof. Davide Bertozzi (U. of Ferrara), is a Best Paper Finalist in the 21st IEEE International Symposium on Asynchronous Circuits and Systems (Async), for their paper "Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters" (May 2015).

• Congratulations to PhD student Kshitij Bhardwaj for obtaining a summer internship at Cadence Design Systems, and to PhD student Weiwei Jiang for obtaining a summer internship at AMD Research!

• Congratulations to PhD students Weiwei Jiang and Kshitij Bhardwaj and former MS student Geoffray Lacourba, for their accepted ACM/IEEE DAC-15 paper on an asynchronous 2D-mesh network-on-chip with early arbitration resolution!

• Professor Nowick is an invited participant in the NSF Workshop on Ultra-Low Latency Wireless Networks (March 2015), a national study group to explore the future of wireless communication for both macro-networks and networks-on-chip (click here).

• Professor Nowick is sub-committee co-chair of the ACM/IEEE Design, Automation and Test in Europe Conference Program Committee (2015), in the network-on-chip area.

• Professor Nowick has joined the editorial boards of IEEE Design & Test Magazine and IEEE Transactions on VLSI Systems, each for a two-year term (January 2015).

• Professor Nowick was invited to 5 Program Committees in 2015: DATE, Async, NOCS, IWLS and INA-OCMC.

2014:

• Welcome to new PhD student Kunal Mahajan, who comes from the UPenn Computer Engineering program! (Fall 2014)

• Professor Nowick is an invited participant in the NSF/DARPA/DOE/NASA Workshop on System-on-Chip Design for High-Performance Computing ("SoC for HPC") (August 2014), a national study group on the future of designing cost-effective high-performance parallel computers for both big data and consumer applications (click here).

• Congratulations to former PhD student Michael Theobald, who is part of the D.E. Shaw Research team winning the 2014 ACM Gordon Bell Prize for best performance of a high-performance computing application, for the Anton 2 Parallel Processor, a special-purpose supercomputer for molecular dynamics simulation!

• Professor Nowick is a selection committee member for the William J. McCalla Best Paper Award for the ACM/IEEE International Conference on Computer-Aided Design (2014).

• Professor Nowick is a selection committee member for the ACM/IEEE "A. Richard Newton Technical Impact Award in Electronic Design Automation" (2014-2015). This annual award honors an outstanding publication with the greatest long-term technical impact in the field of electronic design automation.

• Professor Nowick was invited to 5 Program Committees in 2014: DATE, Async, NOCS, IWLS and INA-OCMC.

2013:

• Professor Nowick gives an invited talk at AMD Research (Boxborough, MA) on his research on asynchronous and GALS networks-on-chip, broadcast to multiple AMD sites (November 2013).

• Congratulations to PhD student Christos Vezyrtzis, who successfully defends his thesis and begins a job as a Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY (May 2013)!

• Professor Nowick is subcommittee chair of the 50th ACM/IEEE Design Automation Conference Program Committee (2011-2013), in the logic- and high-level synthesis and FPGA area. DAC is the leading international conference in design and CAD for electronic systems.

• Professor Nowick is the selection committee chair for the ACM/SIGDA "Outstanding PhD Dissertation in EDA Award" (2012-2013). This international award is provided by the Association of Computing Machinery (ACM), the leading computer science professional society, through its Special Interest Group in Electronic Design Automation (SIGDA), for the best dissertation award in this research area.

• Professor Nowick gives invited talk at the Computer Engineering Eminent Research Seminar series sponsored by the Texas A&M University ECE Department (April 2013).

• Congratulations to PhD student Alberto Ghiribaldi (U. of Ferrara) who, with Prof. Nowick and his advisor Prof. Davide Bertozzi (U. of Ferrara), is a Best Paper Finalist in the ACM/IEEE Design, Automation and Test in Europe (DATE) Conference, for their paper "A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-Effective GALS Multicore Systems" (March 2013).

• Professor Nowick was invited to 6 Program Committees in 2013: DAC, DATE, Async, NOCS, IWLS and INA-OCMC.

2012:

• PhD student Christos Vezyrtzis, with co-advisors Profs. Nowick (CS) and Tsividis (EE), wins Best Paper Award in the Logic and Circuit Design track of the 30th IEEE International Conference on Computer Design (ICCD), for their paper "Designing Pipelined Delay Lines with Dynamically-Adaptive Granularity for Low-Energy Applications" (October 2012).

• Professor Nowick receives an NSF grant to explore and develop dynamically-adaptable on-chip networks (click here for Engineering School profile) (June 2012).

Research Slides:

Overview:

•  "Recent Advances in Designing Clockless Digital Systems" (click here):  A short introduction to asynchronous design, recent industrial developments, and overview of my research.

Networks-on-Chip:

•  "A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors" (click here):  Integrating heterogeneous clocked processors and memories in a shared-memory parallel architecture using a high-performance low-power asynchronous interconnection network.

High-Performance Pipelines:

•  "Introduction to Mousetrap Asynchronous Pipelines" (click here):  Designing high-speed asynchronous pipelines.

Mixed-Timing Interfaces:

•  "Robust Interfaces for Mixed-Timing Systems" (click here):  Designing robust and low-latency interface circuits for mixed-clock and mixed asynchronous/synchronous systems.

Overview Papers:

• D. Bertozzi, G. Miorandi, A. Ghiribaldi, W. Burleson, G. Sadowski, K. Bhardwaj, W. Jiang and S.M. Nowick,   "Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems," (click here)  IEEE Micro Magazine, vol. 41:1, pp. 69-81, Jan./Feb. 2021).

  Provides an introduction to our complete methodology for design low-latency and power-efficient asynchronous on-chip networks. The approach includes: a network-on-chip (NoC) microarchitecture and design, a complete CAD tool flow harnessing synchronous commercial EDA tools, detailed comparisons with synchronous designs in identical technology, and re-implementation at AMD Research (Boxborough, MA) in advanced 14nm FinFET commercial technology. We also provide direct normalized comparisons, for the first time, with some other influential asynchronous NoC designs.

  Our asynchronous design is largely dominating, in comparison to some leading synchronous designs in both academia and industry, in most cost metrics: area, power and performance.

  In comparison to an ultra-low power synchronous NoC using state-of-art clock gating, our async NoC, projected to a full HD video playback application for high-end mobile devices, exhibits up to 45% power improvements and 37% latency savings.

  Moreover, we were invited to collaborate by AMD, and together we reimplemented one of their recent commercial synchronous NoCs in identical advanced (14nm FinFET) technology. Results confirm substantial benefits: 55% lower area, 28% lower latency, and reductions of 88% idle and 58% active power. This is the first apples-to-apples comparison of asynchronous to commercial synchronous general-purpose NoCs in advanced technology.

  [Funding acknowledgment:  The authors gratefully acknowledge the funding support of the National Science Foundation under Grants CCF-1219013 and CCF-1527796.]

• S.M. Nowick and M. Singh,  "Asynchronous Design -- Part 1: Overview and Recent Advances," (click here)  IEEE Design and Test, vol. 32:3, pp. 5-18, May/June 2015).

• S.M. Nowick and M. Singh,  "Asynchronous Design -- Part 2: Systems and Methodologies," (click here)  IEEE Design and Test, vol. 32:3, pp. 19-28, May/June 2015).

  Provides a broad and modern overview of state-of-the-art of the field of asynchronous design. Includes a short history of asynchronous design, as well as a technical introduction to handshaking protocols and data encoding. Also, covers recent industrial successes in mainstream technologies (IBM, Intel, Philips Semiconductors, etc.), as well as recent application to emerging areas (neuromorphic computers, flexible electronics, quantum cellular automata, continuous-time DSPs, ultra-low voltage design, extreme environments). Highlights several application areas in depth, with a wide range of cited publications: GALS systems, networks-on-chip, computer architecture, testing and design-for-testability, and CAD tool development.

  [Funding acknowledgment:  The authors gratefully acknowledge the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606 and OCI-1127361.]

• S.M. Nowick and M. Singh,  "High-Performance Asynchronous Pipelines: an Overview," (click here)  IEEE Design and Test of Computers, special issue on asynchronous design, vol. 28:5, pp. 8-22 (September/October 2011).

  Provides a good basic introduction to asynchronous pipelines. Includes basic background on handshaking protocols, industrial developments, as well as a detailed technical introduction to several leading high-performance pipelines, and their use at Intel, Achronix Semiconductor, and other companies.

  [Funding acknowledgment:  The authors gratefully acknowledge the funding support of the National Science Foundation under Grants CCF-0964606, CCF-0811504 and CCF-0702712.]

Selected Research Papers + Slides:

• W. Jiang, D. Bertozzi, G. Miorandi, S.M. Nowick, W. Burleson and G. Sadowski, "An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart," (click here) ACM/IEEE Design, Automation and Test in Europe Conference (DATE-17), Lausanne, Switzerland (March 2017).

  In collaboration with AMD Research, migrating our asynchronous network-on-chip into advanced 14nm FinFET industrial technology, with a direct head-on-head comparison with an AMD commercial network-on-chip (NoC). This is the first "apples-to-apples" comparison of an asynchronous NoC in advanced technology to a commercial chip. Our asynchronous network-on-chip exhibited dominating results: 55% less circuit area, 28% lower latency, and 58% (/88%) savings in active (/idle) power. For slides, click here.

  [Funding acknowledgment:  The authors gratefully acknowledge the funding support of the National Science Foundation under Grant CCF-1527796, and by the Italian Government through a 'Fondo Giovani' fellowship.]

• G. Miorandi, M. Balboni, S.M. Nowick and D. Bertozzi, "Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow," (click here) IEEE International Symposium on Asynchronous Circuits and Systems (Async-17), San Diego, CA (May 2017).

  An automated tool flow for asynchronous networks-on-chip using synchronous commercial CAD tools (joint with University of Ferrara, Italy).

  [Funding acknowledgment:  The authors gratefully acknowledge the funding support of the National Science Foundation under Grant CCF-1527796.]

Recent Web Articles (grants and tool releases):

• Steven Nowick Invited To Present Work on Asynchronous On-Chip Networks at Two National Study Groups"   -- CS department news story (July 2015)

• Prof. Nowick Developing New Dynamically-Adaptable On-Chip Networks"   -- Engineering School profile on my NSF grant (June 2012)

• Profs. Nowick and Tsividis Developing Ultra-Low Energy Continuous-Time Signal Processors"   -- Engineering School profile on my medium-scale NSF grant (May 2010)

• "Columbia Engineering News":  "Nowick Developing New Desktop Supercomputer"   -- story on my medium-scale NSF team grant, joint with University of Maryland (Summer 2008)

• "EE Times (Europe)"   -- article on our "CaSCADE" Asynchronous CAD Tool Release (December 2007)

• "Columbia Engineering News":  "New Information Technology"   -- cover story on my two Medium-Scale NSF ITR Awards (Fall 2000)

Asynchronous Design in the News...:

•  "Faster Chips That March to Their Own Improvised Beat (click here):   Article in the New York Times, Circuits Section (August 22, 2002). Includes an interview with Professor Nowick.

•  "It's Time for Clockless Chips (click here):   Cover story in  Technology Review Magazine (based in MIT), October 2001, vol. 104:8 (pp. 36-41).  Includes an interview with Professor Nowick.

•  "ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor" (from ARM Ltd. web page, Oct. 2004)