Office:

                Phone:  (212) 939-7056
                FAX:    (212) 666-0140

                E-mail:  nowick AT cs DOT columbia DOT edu
 

I am a Professor of Computer Science and Electrical Engineering, and was former chair of the Computer Engineering Program (2008-2013), at Columbia University.  I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976. My main research interests are:  the design and optimization of asynchronous and mixed-timing (i.e. mixed-clock, asynchronous/synchronous) digital circuits and systems; networks-on-chip (NoC's); low-latency interconnection networks for shared-memory multiprocessors; computer-aided design (CAD) tools; logic synthesis; fault tolerance and reliability; encoding techniques for low-power delay-insensitive communication; and ultra-low power digital systems.

Short Profile of My Research (PDF): (click here) 

Detailed Research Summary (July 2014) (PDF): (click here)  (covers my main research areas, recent papers, technology transfer, grants)

Recent Professional Highlights (2009-present) (PDF): (click here) 

CV's:

• Short CV (journal style)

• Complete CV (August 2014)

Recent News...:

2015:

• Congratulations to PhD students Weiwei Jiang and Kshitij Bhardwaj and former MS student Geoffray Lacourba, for their accepted ACM/IEEE DAC-15 paper on an asynchronous 2D-mesh network-on-chip with early arbitration resolution!

• Professor Nowick is an invited participant in the NSF Workshop on Ultra-Low Latency Wireless Networks (March 2015), a national study group to explore the future of wireless communication for both macro-networks and networks-on-chip.

• Professor Nowick is sub-committee co-chair of the ACM/IEEE Design, Automation and Test in Europe Conference Program Committee (2015), in the network-on-chip area.

• Professor Nowick has joined the editorial boards of IEEE Design & Test Magazine and IEEE Transactions on VLSI Systems, each for a two-year term (January 2015).

2014:

• Welcome to new PhD student Kunal Mahajan, who comes from the UPenn Computer Engineering program! (Fall 2014)

• Professor Nowick is an invited participant in the NSF/DARPA/DOE/NASA Workshop on System-on-Chip Design for High-Performance Computing ("SoC for HPC") (August 2014), a national study group on the future of designing cost-effective high-performance parallel computers for both big data and consumer applications (click here).

• Professor Nowick is a selection committee member for the William J. McCalla Best Paper Award for the ACM/IEEE International Conference on Computer-Aided Design (2014).

• Professor Nowick is a selection committee member for the ACM/IEEE "A. Richard Newton Technical Impact Award in Electronic Design Automation" (2014). This annual award honors an outstanding publication with the greatest long-term technical impact in the field of electronic design automation.

2013:

• Professor Nowick gives an invited talk at AMD Research (Boxborough, MA) on his research on asynchronous and GALS networks-on-chip, broadcast to multiple AMD sites (November 2013).

• Congratulations to PhD student Christos Vezyrtzis, who successfully defends his thesis and begins a job as a Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY (May 2013)!

• Professor Nowick is subcommittee chair of the 50th ACM/IEEE Design Automation Conference Program Committee (2011-2013), in the logic- and high-level synthesis and FPGA area. DAC is the leading international conference in design and CAD for electronic systems.

• Professor Nowick is the selection committee chair for the ACM/SIGDA "Outstanding PhD Dissertation in EDA Award" (2012-2013). This international award is provided by the Association of Computing Machinery (ACM), the leading computer science professional society, through its Special Interest Group in Electronic Design Automation (SIGDA), for the best dissertation award in this research area.

• Professor Nowick gives invited talk at the Computer Engineering Eminent Research Seminar series sponsored by the Texas A&M University ECE Department (April 2013).

• Professor Nowick was invited to 6 Program Committees in 2013: DAC, DATE, Async, NOCS, IWLS and INA-OCMC.

2012:

• PhD student Christos Vezyrtzis, with co-advisors Profs. Nowick (CS) and Tsividis (EE), wins Best Paper Award in the Logic and Circuit Design track of the 30th IEEE International Conference on Computer Design (ICCD), for their paper "Designing Pipelined Delay Lines with Dynamically-Adaptive Granularity for Low-Energy Applications" (October 2012).

• Professor Nowick receives an NSF grant to explore and develop dynamically-adaptable on-chip networks (click here for Engineering School profile) (June 2012).

Research Slides:

Overview:

•  "Recent Advances in Designing Clockless Digital Systems" (click here):  A short introduction to asynchronous design, recent industrial developments, and overview of my research.

Networks-on-Chip:

•  "A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors" (click here):  Integrating heterogeneous clocked processors and memories in a shared-memory parallel architecture using a high-performance low-power asynchronous interconnection network.

High-Performance Pipelines:

•  "Introduction to Mousetrap Asynchronous Pipelines" (click here):  Designing high-speed asynchronous pipelines.

Mixed-Timing Interfaces:

•  "Robust Interfaces for Mixed-Timing Systems" (click here):  Designing robust and low-latency interface circuits for mixed-clock and mixed asynchronous/synchronous systems.

Overview Papers:

• S.M. Nowick and M. Singh,  "High-Performance Asynchronous Pipelines: an Overview," (click here)  IEEE Design and Test of Computers, special issue on asynchronous design, vol. 28:5, pp. 8-22 (September/October 2011).

  Provides a good basic recent introduction to asynchronous design, handshaking protocols, industrial developments, as well as a technical introduction to leading high-performance pipelines, and their use at Intel, Achronix Semiconductor, and other companies.

• C.H. van Berkel, M.B. Josephs and S.M. Nowick,  "Applications of Asynchronous Circuits," (click here)  Proceedings of the IEEE, vol. 87:2, pp. 234-242 (February 1999).

  Provides a basic overview of asynchronous design (less up-to-date but more comprehensive than above paper).

Recent Web Articles (grants and tool releases):

• Prof. Nowick Developing New Dynamically-Adaptable On-Chip Networks"   -- Engineering School profile on my NSF grant (June 2012)

• Profs. Nowick and Tsividis Developing Ultra-Low Energy Continuous-Time Signal Processors"   -- Engineering School profile on my medium-scale NSF grant (May 2010)

• "Columbia Engineering News":  "Nowick Developing New Desktop Supercomputer"   -- story on my medium-scale NSF team grant, joint with University of Maryland (Summer 2008)

• "EE Times (Europe)"   -- article on our "CaSCADE" Asynchronous CAD Tool Release (December 2007)

• "Columbia Engineering News":  "New Information Technology"   -- cover story on my two Medium-Scale NSF ITR Awards (Fall 2000)

Asynchronous Design in the News...:

•  "Faster Chips That March to Their Own Improvised Beat (click here):   Article in the New York Times, Circuits Section (August 22, 2002). Includes an interview with Professor Nowick.

•  "It's Time for Clockless Chips (click here):   Cover story in  Technology Review Magazine (based in MIT), October 2001, vol. 104:8 (pp. 36-41).  Includes an interview with Professor Nowick.

•  "ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor" (from ARM Ltd. web page, Oct. 2004)