STEVEN M. NOWICK

Office:

                Department of Computer Science
                Columbia University
                Room 508, Computer Science Building; Mail Code: 0401
                1214 Amsterdam Avenue
                New York, NY 10027

Phone: (212) 939-7056
FAX: (212) 666-0140

E-mail: nowick AT cs DOT columbia DOT edu

I am a Professor of Computer Science and Electrical Engineering, and chair of the Computer Engineering Program, at Columbia University. I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976. My main research interests are: the design and optimization of asynchronous and mixed-timing (i.e. mixed-clock, asynchronous/synchronous) digital circuits and systems; networks-on-chip (NoC's); low-latency interconnection networks for shared-memory multiprocessors; computer-aided design (CAD) tools; logic synthesis; fault tolerance and reliability; encoding techniques for low-power delay-insensitive communication; and ultra-low power digital signal processors.

Short Profile of My Research (PDF): (click here)

Detailed Research Summary (PDF): (click here) (covers my main research areas, recent papers, technology transfer, grants)

CV's:

Short CV (journal style)

Complete CV (October 2012)

Recent News...:

PhD student Christos Vezyrtzis and co-advisors Professors Steven Nowick (CS) and Yannis Tsividis (EE) win Best Paper Award in the Logic and Circuit Design Track of the 30th IEEE International Conference on Computer Design (ICCD), for their paper "Designing Pipelined Delay Lines with Dynamically-Adaptive Granularity for Low-Energy Applications" (October 2012).

Professor Nowick is subcommittee chair for the 50th ACM/IEEE Design Automation Conference (DAC) Program Committee, for the area of logic- and high-level synthesis and FPGA's (EDA5). DAC is the leading international conference in design and CAD for electronic systems. Prof. Nowick has been invited to serve as subcommittee chair for 2011-2013.

Professor Nowick is selection committee chair for the ACM/SIGDA "Outstanding PhD Dissertation in EDA Award." This international award is provided by the Association of Computing Machinery (ACM), the leading computer science professional society, through its Special Interest Group in Electronic Design Automation (SIGDA), for the best dissertation award in this research area. Prof. Nowick has been invited to serve as chair of the selection committee from 2012-2013.

Professor Nowick will give an invited talk at the Computer Engineering Eminent Research Seminar series sponsored by the Texas A&M University ECE Department (April 2013).

Professor Nowick was invited to 6 Program Committees in 2013: DAC, DATE, Async, NOCS, IWLS and INA-OCMC.

Professor Nowick receives an NSF grant to explore and develop dynamically-adaptable on-chip networks (click here for Engineering School profile) (June 2012).

Research Slides:
Overview:

"Recent Advances in Designing Clockless Digital Systems" (click here):  A short introduction to asynchronous design, recent industrial developments, and overview of my research.

Network-on-Chip:

"A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors" (click here):  Integrating heterogeneous clocked processors and memories in a shared-memory parallel architecture using a high-performance low-power asynchronous interconnection network.

High-Performance Pipelines:

"Introduction to Mousetrap Asynchronous Pipelines" (click here):  Designing high-speed asynchronous pipelines.

Mixed-Timing Interfaces:

"Robust Interfaces for Mixed-Timing Systems" (click here):  Designing robust and low-latency interface circuits for mixed-clock and mixed asynchronous/synchronous systems.

Recent Web Articles (grants and tool releases):

Prof. Nowick Developing New Dynamically-Adaptable On-Chip Networks" -- Engineering School profile on my NSF grant (June 2012)

Profs. Nowick and Tsividis Developing Ultra-Low Energy Continuous-Time Signal Processors" -- Engineering School profile on my medium-scale NSF grant (May 2010)

"Columbia Engineering News": "Nowick Developing New Desktop Supercomputer" -- story on my medium-scale NSF team grant, joint with University of Maryland (Summer 2008)

"EE Times (Europe)" -- article on our "CaSCADE" Asynchronous CAD Tool Release (December 2007)

"Columbia Engineering News": "New Information Technology" -- cover story on my two Medium-Scale NSF ITR Awards (Fall 2000)

Asynchronous Design in the News...:

"Faster Chips That March to Their Own Improvised Beat (click here): Article in the New York Times, Circuits Section (August 22, 2002). Includes an interview with Professor Nowick.

"It's Time for Clockless Chips (click here): Cover story in Technology Review Magazine (based in MIT), October 2001, vol. 104:8 (pp. 36-41). Includes an interview with Professor Nowick.

"ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor" (from ARM Ltd. web page, Oct. 2004)

Clockless Computing: Coordinating Billions of Transistors (Washington University 150th Anniversary Symposium) (click here): Washington University Symposium, St. Louis, Missouri (March 26, 2004). Includes an invited presentation by Professor Nowick.

"Designers Look to Take Computer Chips Off the Clock" (click here): Article in Newsfactor Network (September 18, 2001) on goals and recent achievements of asynchronous design.

"Computing Pioneer Challenges the Clock" (click here) : Article in the New York Times (March 5, 2001) on Ivan Sutherland's group at Sun Microsystems Lab, and their recent advances in developing high-speed asynchronous circuits.

"Old Tricks for New Chips" (click here): Article in The Economist (April 19, 2001) on the promise of asynchronous circuits.

Research Team:

Back row (left to right): Yu Chen, Kshitij Bhardwaj, Steve Nowick, Christos Vezyrtzis, Weiwei Jiang

Front row (left to right): Adil Sadik, George Faldamis

Current PhD Students:

Kshitij Bhardwaj

Yu Chen (EE, co-advised with Prof. Yannis Tsividis)

Weiwei Jiang

Christos Vezyrtzis (EE, co-advised with Prof. Yannis Tsividis)

Current Collaborating PhD Students:

Alberto Ghiribaldi (University of Ferrara [D. Bertozzi group])

Current MS Project Students:

Georgios (George) Faldamis

Adil Sadik

Former Post-Doctoral Research Scientists:

Gennette Gill (D.E. Shaw Research Laboratory, New York, NY)

Former PhD Students:

Melinda Agyekum

Peggy McGee (senior R&D engineer, Power Compiler group, Synopsys Corporation, Sunnyvale, CA)

Cheoljoo Jeong (staff R&D engineer, Verification group, Synopsys Corporation, Mountain View, CA; formerly senior design engineer, Cadence Design Systems, Sunnyvale, CA)

Cheng-Hong Li (became student of Prof. Luca Carloni, now NEC Research Laboratories)

Tiberiu Chelcea (formerly Postdoctoral Fellow, CS Department, CMU)

Robert Fuhrer (IBM T.J. Watson)

Montek Singh (Associate Professor, CS Department, University of North Carolina - Chapel Hill)

Michael Theobald (Researcher, D.E. Shaw Research Laboratory, New York, NY; formerly Postdoctoral Fellow, CS Department, CMU)

Former MS Students: (partial list)

Sumedh Attarde (Server Design group, Intel Corporation, Santa Clara, CA)

Marco Cannizzaro (MS co-advisor; from Politecnico di Torino, Italy)

Walter Dearing

Michael Horak [U. of Maryland, co-chair of MS thesis committee] (Advanced Simulation Technology, Inc.)

Roopa Kakarlapudi

Geoffray Lacourba (ARM Ltd., France)

Amitava Mitra (Intel India)

Ashwath Narasimhan

Harsh Parekh

Srikanth Viswanathan

Former Undergraduate Project Students: (partial list)

Steven Callender (UC Berkeley, PhD Student)

Matthew Carlberg

David Hughes

William Liu

William McLaughlin

Charles O'Donnell (MIT, PhD Student)

Teaching:

Spring 13: CSEE E6861 Computer-Aided Design of Digital Systems

Course Advertisement: (click here)

Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs6861

Fall 12: CSEE W4823 Advanced Logic Design

Course Advertisement: (click here)

Detailed Course Overview: (click here) Class Web Page: http://www.cs.columbia.edu/~cs4823

Office Hours:

Spring-13: Tuesday 2:00-3:00pm, Wednesday 2:45-3:45pm

Room 508, Computer Science Building

phone: (212) 939-7056

ASYNCHRONOUS CAD TOOL PACKAGES

"The CaSCADE Package" is our new asynchronous design environment, including six different tools and libraries. The acronym "CaSCADE" = "Columbia University and University of Southern California Asynchronous Design Environment". It was developed under NSF ITR Award No. NSF-CCR-0086036, with support from additional grants (see CaSCADE web pages for details). This set of asynchronous CAD tools is available for free download for use with Linux platforms.

Three of the tools in the CaSCADE package were developed and maintained by our Columbia asynchronous research group: (a) "MINIMALIST" for asynchronous controllers; (b) the "ATN_OPT Toolset" for robust asynchronous threshold networks; and (c) the "DES (Discrete Event System) Analyzer" for performance analysis and timing verification of concurrent systems.

(a) The MINIMALIST CAD Package, release v2.0: "MINIMALIST" is a comprehensive CAD package for the automated synthesis and optimization of asynchronous controllers. It includes a Verilog back-end, multi-level logic optimizer, decomposition tool for large specifications, verifier, online help and graphical interfaces. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download Minimalist (including extensive tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(b) The ATN_OPT Toolset, release v0.1: The "ATN_OPT" Toolset is a comprehensive CAD package for the automated synthesis and optimization of robust dual-rail asynchronous threshold networks. It supports circuit descriptions in several common formats (Verilog/VHDL/BLIF), and supports cell libraries defined in GENLIB format. It allows several user-specified optimization targets: area, delay, power, and delay-area tradeoffs. It also includes a user shell. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download ATN_OPT (including tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(c) The DES (Discrete Event System) Analyzer, release v0.1: The "DES Analyzer" is a comprehensive CAD package for performance analysis and timing verification of concurrent digital systems. It includes two tools: (i) "DES-PERF" which uses user-supplied stochastic information to compute asymptotic system performance, and (ii) "DES-TSE", which uses user-supplied min/max delay bounds on individual events to compute the global min/max "time-separation-of events" between any two pairs of events. The DES-TSE tool is especially useful in determining which orderings of concurrent events are impossible in the actual global evolution of a concurrent system (going from startup to steady-state) -- potentially useful for optimizing the system -- as well as providing min/max bounds on the system's cycle time (and hence min/max bounds on system throughput). The tool accepts system specifications in the form of a restricted classof Petri net (i.e. "marked graph"), and includes several user options, graphical interfaces, and detailed output reports. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download the DES Analyzer (and tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)