Old tricks for new chips
Apr 19th 2001
From The Economist print edition
Two venerable chip-design techniques, multi-threading and asynchronous logic, are finally on their way to widespread adoption
COMPUTING is similar to cookery. Programs, like recipes, are lists of instructions to be carried out. The raw materials are data which, like vegetables and other ingredients, must be sliced and diced in exactly the right way. Those ingredients must be turned into palatable output as quickly as possible. And in both cases, changes in organisational procedures can produce huge gains in efficiency.
Over the years, the designers of microprocessors have resorted to all sorts of tricks to make their products run faster. Modern chips, for example, queue up several instructions in a “pipeline” and analyse them to see if switching the order in which they are executed can produce the correct result, only more quickly. Similarly, if a recipe says “chop the garlic and heat the stock”, a time-saving chef will start heating the stock first, and then chop the garlic while waiting.
Doing this kind of analysis is worthwhile only if the increase in the complexity of the chip’s design that it requires provides a significant performance boost. Faced with diminishing returns, however, chip designers are dusting down two technologies—called multi-threading and asynchronous logic—that were both invented decades ago. At the time, neither was competitive with conventional designs, but important uses have since emerged for each of them. Multi-threading can increase the performance of database- and web-servers, while asynchronous logic is ideal for wireless devices and smartcards. As a result, both technologies are now heading towards the marketplace.
The idea of multi-threading goes back to the 1960s, and its use in supercomputers has been championed by Burton Smith, the chief scientist at Cray, a supercomputer maker. In 1995 Susan Eggers, Hank Levy and Dean Tullsen at the University of Washington showed how the idea could be applied to mass-market microprocessors, in a technique called “simultaneous multi-threading” (SMT). What makes SMT particularly clever is that a small increase in a chip’s complexity results in a vast improvement in its performance, with one proviso: the gain comes when the chip is running lots of programs at once. In practice, though, all modern computers do this—users expect, for example, to be able to run a web browser and a word processor while listening to an MP3 music file. Strictly speaking, these programs are not actually operating at the same time. Instead, a single processor runs one program for a few milliseconds, then switches to another. But this switching happens so quickly that the user is fooled into thinking that all the programs are working simultaneously.
Inside the processor, this switching between programs looks a lot less slick. Switching involves storing the “processor state” for the outgoing program (that is, the configuration of the functional units that do the actual calculations), restoring the processor state for the incoming program, and then resuming operation. This is rather like a chef preparing (say) eight recipes at once by working on each for (say) three minutes at a time, and then switching recipes. Every time he switches, he has to forget the old recipe, re-read the new one, and move all of the ingredients on and off his chopping board.
SMT works by giving the chef a larger chopping board and allowing him to interleave steps from all eight recipes, while still ensuring that the peas end up in the pea soup. An SMT chip keeps track of several programs, or “threads”, at once. Doing so requires extra hardware to store the processor state for each thread, and when instructions are added to the queue, they must be labelled as coming from a particular thread. That way, when an instruction is sent to one of the various number-crunching units on the chip, it knows which thread’s state to update with the result.
Engineers at Compaq, an American computer maker, have estimated that only about 10% more circuitry is needed to enable a conventional chip design to support four threads at once in this way. But the improvements in performance can be spectacular, because when one of the threads is held up waiting for data to arrive, the others can keep running. Database- and web-servers generally create a separate thread for each user request—so the ability to run several threads simultaneously is a particular advantage for them. Simulations run by Dr Eggers’s team have found that an eight-thread SMT chip could run database software three times faster than a conventional chip, and web-server software four times faster. And those figures, says Dr Eggers, are for unmodified software. Tweaking the programs to support SMT explicitly could, she suggests, speed things up even more.
Where SMT offers chip designers a big performance gain for a relatively small design change, asynchronous logic involves a far more dramatic rethink. As its name suggests, it does away with the cardinal rule of chip design: that everything marches to the beat of an oscillating crystal “clock”. For a 1GHz chip, this clock ticks one billion times a second, and all of the chip’s processing units co-ordinate their actions with these ticks to ensure that they remain in step. Asynchronous, or “clockless”, designs, in contrast, allow different bits of a chip to work at different speeds, sending data to and from each other as and when appropriate.
The idea of asynchronous logic goes back to the dawn of digital computers. Some of the earliest machines (built in the 1950s) were based on clockless designs. But the synchronous approach predominated, largely because it is easier to design chips in which things happen only when the clock ticks. In recent years, however, clockless designs have started to look more appealing. One reason is that, as chips get bigger, faster and more complicated, distributing the clock signal around the chip becomes harder. Another drawback with clocked designs is that they waste a lot of energy, since even inactive parts of the chip have to respond to every clock tick. Clocked chips also produce electromagnetic emissions at their clock frequency, which can cause radio interference.
There are several styles of asynchronous design, according to Steve Furber, a computer scientist at Manchester University in Britain. Whereas conventional chips represent the zeroes and ones of binary digits (“bits”) using low and high voltages on a particular wire, one clockless approach, called “dual rail”, uses two wires for each bit. A sudden voltage change on one of the wires represents a zero, and on the other wire a one. Another approach is called “bundled data”. Low and high voltages on 32 wires are used to represent 32 bits, and a change in voltage on a 33rd wire indicates when the values on the other 32 wires are to be used.
Asynchronous designs take up more room on a chip than conventional designs, and there are far fewer design tools available to help create them, but a number of groups, including Dr Furber’s, have already built asynchronous microprocessors. Ivan Sutherland of Sun Microsystems, who is regarded as the guru of the field, believes that such chips will have twice the power of conventional designs, which will make them ideal for use in high-performance computers. But Dr Furber suggests that the most promising application for asynchronous chips may be in mobile wireless devices and smartcards.
Wireless devices based on asynchronous chips would run for longer between recharges, and their circuitry would cause less radio interference. Dr Furber is developing asynchronous chips for such devices in conjunction with ARM, a British company whose processors appear in many handheld computers and mobile phones. Philips, a Dutch electronics firm, has already built a pager that uses asynchronous logic, and Theseus Logic of Orlando, Florida, is also pursuing low-power wireless applications.
In the case of smartcards, Dr Furber suggests that asynchronous logic would offer better security than conventional chips. The encryption on existing smartcards can be cracked by analysing the power consumption for each clock tick. This allows details of the chip’s inner workings to be deduced. Such an attack would be far more difficult on a smartcard based on asynchronous logic.
There is, of course, a catch. Both SMT and asynchronous logic undermine the use of a chip’s clock speed as a proxy for its performance. And that might make things tricky for the marketing men, who have long insisted that the more MHz, the merrier.
|OPINION | WORLD | BUSINESS | FINANCE &
ECONOMICS | SCIENCE &
PEOPLE | BOOKS & ARTS | MARKETS & DATA | DIVERSIONS | PRINT EDITION
© Copyright 2001 The Economist Newspaper Limited. All rights reserved.