Alan Smith

Joseph Zuckerman

Computer Science PhD Student

About

I am a second year PhD student in the System Level Design group in the Computer Science department at Columbia University, focusing on heterogeneous system-on-chip architectures. My research interests include novel architectures, runtime management, and agile design techniques for many-accelerator systems-on-chip.

In 2019, I completed a Bachelors of Science in Electrical Engineering from Harvard University. At Harvard I studied computer hardware across the full-stack, learning architecture, circuits, VLSI, systems, algorithms, and applications, and, in particular, focused on the design of architectures for machine learning applications.

Education

Columbia University

PhD, Computer Science (Expected: Dec 2024)

  • Currently supported by a National Science Foundation Graduate Research Fellowship, previously supported by a Columbia SEAS Presidential Distinguished Fellowship

MS, Computer Science (April 2021)

  • 4.0/4.0 GPA

Harvard University

S.B, Electrical Engineering (May 2019)

  • Magna Cum Laude with Highest Honors in Field
  • Phi Beta Kappa

Publications

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni
IEEE/ACM International Symposium on Microarchitecture (MICRO-54), 2021

Agile SoC Development with Open ESP

Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020 (invited)

Projects

A product of many years of research from the SLD group at Columbia, ESP is an open-source platform for heterogeneous SoC design and prototype on FPGA. It provides a flexible tile-based architecture built on a multi-plane network-on-chip.

In addition to the architecture, ESP provides users with templates and scripts to create new accelerators from SystemC, Chisel, and C. The ESP design methodology eases the integration process by offering platform services, such as DMA, distributed interrupt, and run-time coherence selection, that hide the complexity of hardware and software integration from the accelerator designer.

EPOCHS

A collaboration between IBM, Columbia, Harvard, and UIUC, the EPOCHS project is funded within the DARPA Domain-Specific System-on-Chip (DSSOC) program. EPOCHS is part of an effort to enable the rapid development of multi-application systems through a single programmable device.

Work Experience

NVIDIA

ASIC Design Intern

June - August 2019

  • RTL Design work in the memory subsystem for mobile SOCs

Hardware Verification Intern

June - August 2018

  • Extended Verilog and C++ behavioral model for interconnect

Harvard University

Undergraduate Research Assistant

January 2018 - May 2019

  • Accelerators for machine learning algorithms

Teaching Fellow

August 2017 - May 2019

  • CS 141 - Computing Hardware: held office hours, created and graded assignments, taught sections and lectures

NASA Jet Propulsion Lab

Electrical Engineering Research Intern

June - August 2017

  • Low power circuits for micro mercury atomic clock

NoiseAware

Hardware/Software Engineering Intern

June - August 2016

  • Firmware implementation and debugging for smart in-home noise monitors