Gabriele Tombesi

Computer Science PhD Student

I am a second year PhD student, part of the System-Level Design Group at Columbia University. My Research interests include HLS-based design flows for hardware acceleration of Deep Learning workloads and Design for Testability techniques for heterogeneous system-on-chip architectures. I am currently focused on the integration of the Catapult HLS - SystemC Design flow into the open-source ESP project developed by my group. 

I received the joint M.S. degree in Electrical Engineering from the Politecnico di Torino, École Polytechnique Fédérale de Lausanne and Grenoble INP and the B.S. degree in Physical Engineering from the Politecnico di Torino.


Google Scholar



B.Sc. in Physical Engineering (October 2018)

M.Sc in Electrical Engineering (October 2020)

Ph.D. in Computer Science (Excpected: Jul 2026)





A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Block s, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
Tianyu Jia, Paolo Mantovani, Maico Cassel Dos Santos, Davide Giri,Joseph Zuckerman, Erik Je
ns Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Cahndromoorthy, John-David Wellman, Kevin Tien, and Luca P. Carloni
In Proceedings of the European Conference on Solid-State Circuits (ESSCIRC), 2022.

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.
Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel Dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P Carloni.
In  IEEE Design & Test 2023 - NOCS’23 Special Issue - Best Paper Award.

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Maico Cassel Dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca Carloni, and Pradip Bose.
In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), 2022.

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
F. Gao, T.-J. Chand, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, Joseph Zuckerman, J. Tu, K. Xu, G. Chirkov, Gabriele Tombesi, J. Balkind, M. Martonosi, L. Carloni, and D. Wentzlaff.
In Proceedings of the Custom Integrated Circuits Conference (CICC), 2023.


Work Experience