Giuseppe Di Guglielmo


I am currently involved in the following projects and research centers:

  • SHF: Small: Rethinking CAD for System-Level Design via Interactivity, Learning, and Collaboration, June 15, 2015 (Award Number: 1527821)
    • A core part of this program is the development of a new senior-level undergraduate course that will engage the students in working together on a semester-long project with the infrastructure support for collaborative engineering provided by the new CAD environment. Current effort of designing state-of-the-art integrated circuits, suffers from shortcomings that characterize current CAD flows, e.g., the lack of support for exploring the design space across its hardware and software components in search of better solutions; the limited capabilities in optimizing simultaneously multiple components at the system level; and the big learning curve and long execution times that many tools require. This project will investigate a new generation of CAD methodologies and tools. Specifically, the research team will develop a new environment for System-Level Design that is highly interactive, exalts the designers' experience, inspires their creativity, and promotes continuous collaboration across the engineering team. The proposed approach leverages recent work on supervised and compositional design-space exploration, and the application of learning methods to assist designers in the use of advanced high-level synthesis tools.
  • PERFECT, January 4, 2013 (Solicitation Number: DARPA-BAA-12-24)
    • The goal of DARPA’s Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program is to seek revolutionary approaches and to research and develop the technologies and techniques that will provide the power efficiency required to enable embedded computing systems. The PERFECT program addresses seven program elements. Five of these--Architecture, Concurrency, Resilience, Locality, and Algorithms--comprise the primary research thrusts. The remaining two, Simulation and Test and Validation, are essential support activities. This combination of technologies, coupled with anticipated industry fabrication geometry advances to 7 nm, is intended to enable the PERFECT program to attain 75 GFLOPS/W, one of the PERFECT program’s goals as stated in the original PERFECT Broad Agency Announcement.
  • C-FAR
    • The Center for Future Architectures Research (C-FAR) is a research center focused on innovation to create future generation scalable computing systems. The center is working on research that maximally leverages emerging circuit fabrics to enable whole new application areas. It accomplishes this goal through a highly collaborative research agenda that brings together researchers from many universities, including Michigan, Columbia, Duke, Georgia Tech, Harvard, MIT, Northeastern, Princeton, Stanford, UC Berkeley, UCLA, UC San Diego, Illinois, Washington and Virginia.
    • The Center is funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA) through the Semiconductor Technology Advanced Research network (STARnet). The center resides at the University of Michigan.

These are some projects I was involved in:

  • VERTIGO, June 1, 2006 (Project reference: 033709, Funded under: FP6-IST)
    • VERTIGO dealed with the development of technologies and tools to integrate verification of embedded systems built upon configurable platforms, within economical and technical constraints. VERTIGO exploited results and tools coming from the IST-FP5 SYMBAD project and widens the spectrum of formal techniques applied at the verification of embedded systems.
  • COCONUT, January 1, 2008 (Project reference: 217069, Funded under: FP7-ICT)
    • The aim of the project was the definition of a formal framework based on tight integration of design and verification through all refinement steps of an embedded platform design flow, from specifications to logic synthesis and software compilation. In particular, it proposes a modeling and verification flow that enhances and speeds up embedded platform design and configuration and address mixed continuous/discrete models such as networked multimedia and sensor network management.