Giuseppe Di Guglielmo


This is my curriculum vitae (last updated February 24, 2017).

Research interests

Main research interests concern system-level design, electronic design automation methodologies for modeling, verification, testing and optimization of hardware and software systems. Current research topics are design and validation of hardware and software components for machine learning system-on-chips, including high-level synthesis and FPGA prototyping.

Knowledges and background

Functional qualification based on mutation analysis; simulation, emulation, and co-simulation for platform models; formal and simulation-based techniques for design state space exploration; assertion-based verification for hardware and software components; automatic test pattern generation for behavioral and RTL descriptions; functional faults models and parallel fault simulation; computational models in the digital design area; model-driven design and validation of embedded software; dynamic property mining for embedded software and system-level descriptions; supervised and unsupervised learning (regression techniques, neural networks, support vector machines).

Programming and skills

C/C++, Python, TensorFlow, SystemC (TLM), SystemC Verification Library, UVM, VHDL, Verilog, TCL, OpenMP, Latex, Bash, Cadence C-to-Silicon, Cadence Design Compiler, Cadence Incisive Enterprise Simulator, Mentor Graphics ModelSim, Synopsys Certitude Functional Qualification System, Wind River Simics, QEMU.


  • Ph.D. in Computer Science, April 2009
  • Laurea degree in Computer Science Magna cum Laude, September 2005
    • Verifica funzionale dei dispositivi digitali mediante manipolazione di Macchine a Stati Finiti Estese
    • University of Verona – Faculty of Mathematical, Physical and Natural Science
  • Classical Studies Diploma, July 1998
    • Liceo Ginnasio di Stato Scipione Maffei, Italy


  • Machine Learning by Stanford University on Coursera (Prof. Andrew Ng).

Academic experiences and employment history