READ: 6.8 pp. 239-46), 6.2.7 (p. 183-5)
PROBLEMS: 6/(54, 55, 13)
READ: 4.1.2 (p. 109) MUX, 6.4.2 (p. 196) Latch, 6.2.6 (p. 177) Combinational hazards, 6.2.8 (p 185) Essential hazards.
PROBLEMS:6/(23, 25, 26, 29)
Problems: In same handout. 2/(3, 15, 5-7)
Problems: (In handout) 2/(9-12). (In text) 5/(9, 11, 12)
Problems: IN TEXT 5/(14-16, 19)
NON-TEXT Implement the flow table for the two's complement function in tree form. You need only specify the logic for the primary and interior modules after finding the set of mappings and generating the multiplication table for the mappings.
1. Design a simple linear iterative circuit for the comparator. Pay special attention to the last module, where the output signal must be produced.
2. Design a simple tree-realization of the comparator. Note that the tree will be simpler than for a circuit such as an adder, where we need a sequence of outputs, rather than just a single output. Think carefully about what the primary level and interior modules need to do in this situation, so you can avoid doing unnecessary work and specifying useless logic. Pay particular attention to how best to generate the output signals.
3. Design a linear iterative circuit with a completion signal. Assume dual-rail inputs. Use 1-hot coding for the state assignment.
4. Show the design of a Brent-Kung adder for 8-bit numbers. Draw a
block diagram with all the primary level, interior and output
generating modules. Specify logic expressions for each type of
NT-1. For each of the following two expressions, identify any
static combinational hazards that exist in the corresponding 2-stage
logic circuits, assuming SIC operation.
NT-2. Design 32-bit speculative completion adders meeting each of the following specifications. Assume the body of the adder is of the ripple-carry type and that there is 1 unit of delay for each adder stage. (a) The completion signal is generated with delay 32 (worst case) or with delay 17. Use 2 p-signals. (b) The completion signal is generated with delay 32, or 17, or 12. Use 2 p-signals to control the delay of 17, and 4 p-signals to control the delay of 12.
NT-3. Using as building blocks full adders and half adders, as well as a single block representing a fast 5-bit adder with carry out, draw a diagram of an array multiplier based on the carry save adder idea, that will multiply two 5-bit numbers. Assume as inputs, the 1-bit products, pij, where pij=AiBj.
NT-4. Construct a tree of CSA's to add 32 numbers. Don't worry about bit positions. Represent each adder (k-bits) by an oval. Terminate with a rectangle, representing a conventional adder that generates a single number for its output. There is no unique solution to this problem, but you should not have trouble finding a tree whose maximum depth, INCLUDING the conventional adder, is 8.
HW # 8
Problems: In text 6/(47-51)
Read first 5 sections of Notes on Linear Sequential Circuits, now posted on the class website.
In all these problems, + means XOR
1. Solve the following set of linear equations for the Xs in terms of the Zs.
Z1 = X1 + X3 Z2 = X1 + X2 Z3 = X1 + X2 + X3 2. Find all the null sequences of each of the following polynomials (a) D3 + D + I (b) D4 + D3 + D2 + D + I 3. Find the polynomial for which the following is the m-sequence (maximal length null sequence). 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1. 4. Factor the following polynomials: (a) D6 + D4 + I (b) D5 + D4 + D2 + I 5. Show that if S is any m-sequence, then S^R, (S written backwards) is also an m-sequence. Indicate how the corresponding polynomials are related.
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