Rainbow Apple LogoAltera DE2 board
Apple2fpga: Reconstructing an Apple II+ on an FPGA
Stephen A. Edwards
Columbia University

As a Christmas present to myself in 2007, I implemented an 1980s-era Apple II+ in VHDL to run on an Altera DE2 FPGA board. The point, aside from entertainment, was to illustrate the power (or rather, low power) of modern FPGAs. Put another way, what made Steve Jobs his first million can now be a class project for my 4840 embedded systems class.

What is an Apple II?

Inside an Apple II

The Apple II was one of the first really successful personal computers. Designed by Steve Wozniak ("Woz") and first introduced in 1977, it really took off in 1978 when the 140K Disk II 5.25-inch floppy drive was introduced, followed by VisiCalc, the first spreadsheet program.

Fairly simple even by the standards of the day, the Apple II was built around the inexpensive 8-bit 6502 processor from MOS Technology (it sold for $25 when an Intel 8080 sold for $179). The 6502 had an eight-bit data bus and could access 64K of memory. In the Apple II, it runs at slightly above 1 MHz. Aside from the ROMs and DRAMs, the rest of the circuitry consisted of discrete LS TTL chips.

While the first Apple IIs shipped with 4K of DRAM, this quickly grew to a standard of 48K and later to 64K through the help of bank switching and an memory expansion card. DRAMs, at this time, were cutting-edge technology. While they were difficult to use, requiring +5, +12, and -5V power supplies and needing to be periodically refreshed, their roughly six-times improvement in density made it worthwhile. Breathless copy in an early ad for the Apple I touted their advantages.

While the Apple II came with an integrated keyboard, a rudimentary (one-bit) sound port, and a game port typically connected to a two-axis analog joystick, its main feature was its integrated video display. It generated composite (baseband) NTSC video that was usually sent through an RF modulator to appear on e.g., a TV's channel 3.

The Apple II had three video modes: a 40 X 24 uppercase-only black-and-white text display, a 40 X 48 16-color low-resolution display, and a 140 X 280 6-color high-resolution display.

The Apple II can almost be thought of as a video display device that happens to have a microprocessor connected to it. Woz started with a 14.31818 MHz master pixel clock -- exactly four times the 3.579545 MHz colorburst frequency used in NTSC video. Because of the way color was added to the black-and-white NTSC standard, seemingly black-and-white patterns sent at exactly this frequency are interpreted as color.

Woz derived the CPU clock from the 14.31818 MHz clock by dividing by roughly fourteen. I say roughly because in fact every sixty-fifth CPU cycle (once per horizontal scan line) is stretched by two 14 MHz clock periods to preserve the phase of the 3.58 MHz colorburst frequency. Thus, there are 65 * 14 + 2 = 912 pixel periods per line, or exactly 228 cycles of the 3.58 MHz colorburst per line.

Both the CPU and video access a byte of memory at 1 MHz. Their accesses are interleaved, so the DRAM effectively operates at 2 MHz. Another Woz trick: the video addresses are such that refreshing the video also suffices to refresh the DRAMs, so no additional refresh cycles are needed.

In my reconstruction, I tried to reproduce the behavior of the timing circuitry (including the stretched cycle) as closely as possible. However, rather than actually generate lower-frequency clocks in this way (generally a bad idea in modern designs, where the use of on-chip PLLs with skew control is the preferred technique), I ran most of the core at the 14 MHz clock and distributed latch enable signals to anything that was originally clocked at one of the derived frequencies.


My Reconstruction

My Apple II core consists of a timing generator, a video generator, the 6502 processor core, which I took from Peter Wendrich's Commodore 64 emulator, the ROMS, and some random logic for address decoding and other onboard I/O. Broadly, the core expects a 14.31818 MHz clock signal, input from the keyboard, access to a 64K RAM, and access to the peripheral bus (currently, just a disk drive emulator) and generates a one-bit video stream along with one bit of audio data for the speaker.

To make this core usable, I attached to it a PS/2 keyboard controller (from Alex Freed and ALSE), a disk emulator, and a VGA line-doubler that converts the 15 kHz horizontal refresh rate of the Apple's one-bit video output to a color VGA output with 30 kHz horizontal refresh rate.

The line doubler contains memory for two lines of video from the Apple; I display one twice while the other is being read from the Apple's video out. In additional to interpreting and generating the horizontal and vertical syncronization signals, it converts the one-bit video stream to color using a probably overly-simple algorithm: every four 14 MHz pixels are interpreted as a block and displayed as a single color. This is reasonably effective, and produces many of the odd color fringing effects of the original Apple II, but is not quite right since a true television set actually performs more gentle low-pass filtering on the luimance and chrominance signals. A better algorithm would consider bits adjacent to each group of four. Nevertheless, the display is certainly usable.

Apple II text mode Apple II lores mode Apple II hires mode

My emulation of the Disk II is primitive (read-only) but functional. I store a "nibblized" image of a 5.25-inch floppy on an external SD card and read it into on-chip memory a track at a time. I coded an SPI interface (one of the three spoken by typical SD cards) in VHDL that is able to wake up the card and download random 256-byte blocks. Controlling this is a simple emulator for the Disk II controller, which provides a very low-level interface to the drive. For example, the read/write head is moved under software control by selectively pulsing four stepper motor phases. My hardware emulator watches these pulses, and models on which track the head currently resides.

Each time the track number changes, my controller reads from the SD card a new group of 6655 bytes (256 * 25) into track memory. Meanwhile, I emulate the spinning disk by periodically changing the address of the data read by the CPU when it accesses the disk I/O locations.

For debugging, I brought out the CPU's PC to four of the seven-segment displays on the board and the current track for the drive on another two. While the PC is usually changing so fast it becomes a blur, patterns do often emerge. For example, the PC remains highly focused when the computer is waiting at the prompt. Similarly, I have found a lot of software, including the operating system when it is moving the drive head, calls the monitor's "delay" routine to slow things down.

Comparing Implementations

Kill A Watt power meter

A central motivation for this project was to illustrate how integrated modern FPGAs have become and how comparatively little power they consume. So I compared the power consumed by an actual Apple II+, an Apple II+ emulated in software, and my FPGA reconstruction.

To measure power, I used the inexpensive and very easy to use "Kill A Watt" power meter. This claims 0.2% accuracy, which is plenty to get a rough idea of what (watt?) is going on.

In each case, I measured the power consumed by the system excluding the monitor. The power was more-or-less constant for the Dell (while the emulator was running) and FPGA board; the Apple II's power consumption varied considerably when the disk was active (spinning).

Only the number for the Apple II is really fair. The Dell is freakishly overpowered, had far more memory (192 MB) than necessary to run Linux and the Apple II emulator, and never used its floppy drive, CD ROM, etc. The FPGA board has similar problems: it also has (unused) Ethernet, USB, and NTSC video interfaces as well as SDRAM and Flash chips. While none were running, they still consumed some power.


An Apple II+ An Apple II+ emulated in software An Apple II+ on an FPGA
An Apple II+ An Apple II+ on a Dell An Apple II+ on an FPGA
22W 62W 5W
31W (Disk active)
Apple II+ Dell Optiplex GXa Altera/Terasic DE2
c. 1982 c. 1998 c. 2006
Synertek 6502 Intel Pentium II Altera EP2C35F672C6 Cyclone II
LS TTL, 16K DRAMs, 1 MHz NMOS CPU 233 MHz, 250 nm CMOS CPU 90 nm CMOS
CPU: 4K transistors? CPU: 7.5M transistors 33K LEs, 150M transistors?

Technical Resources

The Apple II has been documented in great detail. Starting with the first Apple II "Redbook" Reference Manual, Apple itself has published the schematics for the Apple II series. When Woz spoke at Columbia, he mentioned this was intentional: he wanted to share as much technical information as possible to educate the users. Such an attitude is rare these days.

Two third-party books provide even more detailed commentary: Winston Gayler's The Apple II Circuit Description (Sams, 1983), and Jim Sather's Understanding the Apple II (Quality Software, 1983). I consulted both frequently while writing the VHDL for this project. For understanding the Disk II and more precisely, Apple's disk operating system (DOS 3.3), Don Worth and Pieter Lechner's Beneath Apple DOS (Quality Software, 1983) is second to none, although it is much more software-focused than the first two books.

All of these books are long out-of-print, but some have been scanned and archived on the web. 1000bit.net has an especially nice collection.

Alex Freed's FPGApple project inspired this one. Alex was kind enough to share his source code with me (it was not as bad as he claims on his website) and I used it as reference as I was writing my own.

Downloads

Retrocomputing on an FPGA: Reconstructing an 80's-Era Home Computer with Programmable Logic, a technical report on the project.


apple2fpga-1.1.zip


apple2fpga-0.1.tar.gz


This contains all the VHDL source as well as some scripts, utility programs, and a bootable disk image. It is ready to compile with Altera's Quartus system for the DE2 FPGA board. Other boards or other environments will require some adaptation.

Translations

View this page in Romanian courtesy of azoft

View this page in German (Deutsch) couresy of Valeria Aleksandrova.

View this page in Polish couresy of Olga Babenko.

Danish translation by ScienceLakes