Gabriele Tombesi
Ph.D. Candidate in Computer Science
I am a Ph.D. candidate in Computer Science at Columbia University, advised by Prof. Luca P. Carloni in the System-Level Design Group. My research focuses on computer architecture and hardware/software co-design for efficient AI inference, with an emphasis on runtime-reconfigurable tiled accelerators, workload mapping, data movement, and system-level optimization. My recent work explores Transformer and LLM inference, including speculative decoding, as well as high-productivity methodologies for accelerator and heterogeneous SoC design.
I have also gained industry experience through internships at Tenstorrent, working on low-level AI inference optimization, and NVIDIA Research, working on HLS-based accelerator design.
I received the joint M.S. degree in Electrical Engineering from the Politecnico di Torino, École Polytechnique Fédérale de Lausanne, and Grenoble INP, and the B.S. degree in Physical Engineering from the Politecnico di Torino.
Education
- Polytechnic of Turin
B.Sc. in Physical Engineering (October 2018)
- Polytechnic of Turin-INP-EPFL
M.Sc. in Electrical Engineering (October 2020)
- Columbia University
Ph.D. in Computer Science
Jan 2021 – Expected May 2027
HOME
Selected Research Projects
- SPECTRA [paper]
A runtime-reconfigurable tiled architecture for speculative decoding that adapts execution, workload partitioning, and on-chip communication across different phases of LLM inference. Accepted at ICCAD 2026.
- FLIP2M / OASIS [GitHub]
A flexible tiled architecture and mapping framework for multi-model AI inference. OASIS explores resource allocation, workload partitioning, and pipelined execution to improve accelerator utilization across heterogeneous workloads. Published in ACM TECS/CASES 2025.
- ESP
ESP is an open-source platform for research on heterogeneous system-on-chip design. My work has included accelerator integration, SystemC/HLS design flows, NoC-based accelerator communication, and FPGA prototyping.
- SoCProbe
A compositional methodology for pre- and post-silicon validation of heterogeneous NoC-based SoCs, including distributed debug infrastructure integrated into ESP and validated on silicon. The work received the NOCS’23 Special Issue Best Paper Award.
Selected Publications
SPECTRA: Adaptive Execution of Speculative Decoding on a Runtime-Reconfigurable Tiled Architecture
Gabriele Tombesi, William Baisi, Je Yang, Elisavet Lydia Alvanaki, Kevin Lee, Michael Lippe, Biruk Seyoum, Luca P. Carloni.
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026. [arXiv]
A Coherence-Aware Runtime Reconfigurable System-on-Chip for Efficient Language Model Inference
Je Yang, Gracen Wallace, Joseph Zuckerman, Gabriele Tombesi, Luca P. Carloni.
IEEE Micro, 2026. [PDF]
FLIP2M: Flexible Intra-layer Parallelism and Inter-layer Pipelining for Multi-model AR/VR Workloads
Gabriele Tombesi, Je Yang, Joseph Zuckerman, Davide Giri, William Baisi, Luca P. Carloni.
ACM Transactions on Embedded Computing Systems (TECS), CASES, 2025. [PDF]
Teaching Collaborative SoC Engineering with HLS-Based Accelerator Design and Agile System-Level Integration
Gabriele Tombesi et al.
Workshop on Computer Architecture Education (WCAE), 2025. [PDF]
ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers
Je Yang, Gabriele Tombesi, Joseph Zuckerman, Luca P. Carloni.
International Conference on Field-Programmable Logic and Applications (FPL), 2025. [PDF]
EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation
Joseph Zuckerman et al., including Gabriele Tombesi.
IEEE Journal of Solid-State Circuits (JSSC), 2025 (early access). [DOI]
A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
Maico Cassel dos Santos et al., including Gabriele Tombesi.
IEEE International Solid-State Circuits Conference (ISSCC), 2024. [DOI]
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs
Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni.
IEEE Design & Test, NOCS’23 Special Issue, 2023 — Best Paper Award. [PDF]
Full publication list on Google Scholar
Work Experience
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Columbia University
Graduate Research Assistant
January 2021 – Present
New York City
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Tenstorrent
AI Hardware Intern
May 2026 – August 2026
Zurich, Switzerland
Developed and optimized multicore AI inference kernels on Tensix NEO, including matrix multiplication and FlashAttention, with a focus on workload partitioning, on-chip data movement, synchronization, and multicore scaling.
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NVIDIA Research
Summer Research Intern
May 2024 – August 2024
Santa Clara, CA
Worked on HLS-based accelerator design and parameterized SystemC hardware generation for computer-vision workloads, using Catapult HLS and MatchLib.
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Columbia University
Teaching Assistant for
System-on-Chip Platforms (CSEE W4868)
September – December 2022
New York City
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Columbia University
Research Intern
March – October 2020
New York City
Design of a debug unit that provides a flexible, platform-based pre- and post-silicon verification methodology to address the increasing complexity of modern heterogeneous systems-on-chip (SoCs).
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IBM
Nanofabrication and
Characterization Intern
June – August 2019
San Jose
Processing of vacuum-deposited metal oxide semiconductor (MOS) films and testing of their electrical and sensing properties, targeting orthogonal response when exposed to specific volatile organic compound mixtures.
