Davide Giri

Ph.D. Candidate in Computer Science

Ph.D. Candidate in Computer Science at Columbia University, part of the System-Level Design Group. Research interests include architectures and system-level design methodologies for heterogeneous system-on-chip, with particular focus on hardware accelerators.

Project Mentoring

Spring 2021
Gabriele Tombesi
A Vertical Testing Infrastructure for Deep Learning Accelerators
Sammy Almawaldi
Design of a Low Power JPEG Decoder with Vivado HLS
William Pflueger
JPEG Hardware Acceleration
Fall 2020
Pratyush Agrawal
Design of a Harware Accelerator for DCT/IDCT using Vivado HLS
Summer 2020
Pei Liu
Design of an Accelerator for Computing the MRI-Q Matrix with Vivado HLS
Pratyush Agrawal
Design of an Accelerator for the Cholesky Decomposition
Spring 2020
Xiangyu Zhao
Design of an Accelerator for Backpropagation
Caleb Rees Tulloss
Accelerated Linear Autoencoder Training for Neural Spike Localization
Jun Sha
Accelerator Design for Genomic Sequence Alignment Based on Dynamic Programming
Pei Liu
Design of an Accelerator for Computing the MRI-Q Matrix
Ayushparth Sharma
Re-configurable AES Accelerator for Heterogeneous SoC Design using the ESP Platform
Maico Cassel dos Santos
Power Analysis Estimation Flow for Accelerator Designs
Doga Ozesmi
A Floating-Point Unit for ESP
Shabhari Saravanan
Design of an Accelerator for Sum of Absolute Differences
Pratyush Agrawal, Sonali Medani
Design of a Hardware Accelerator for Principal Component Analysis
Xiaofu Pei
Design of an Accelerator for 3D Stencil Computation
Qayyoom Arieff
Hardware-accelerated Spiking Neural Network using ESP
Joseph Zuckerman
Learning Optimal Cache Coherence and Memory Allocation Policies in Heterogeneous SoCs
Yung-Ching Lin
Design of Secure Hash Algorithm Accelerators for ESP
Anton Nefedenkov
RAS: Resource Access Scheduler for Accelerator Private-Local Memories
Fall 2019
Tushar Kant Roy
HLS Implementation of an Accelerator for Motion Estimation
Spring 2019
Guy Eichler
Integration of the NVDLA Accelerator into the ESP Framework
Chengqi Dai, Xuyang Liu
Multi-Function Accelerator for Matrix Operators
Tushar Kant Roy
Machine Learning Algorithm for Runtime Reconfigurable Memory Hierarchy
Lancelot Wathieu
Design of an Accelerator for Saturated Histogramming
Kuan-lin Chiu
Design of a Night-Vision Accelerators for ESP
Fall 2018
Danfeng Yang
Applications Profiling: 3D Segmentation with Flood-Filling Networks and Global Vectors for Word Representation (GloVe)
Kaustubh Chiplunkar
Applications Profiling: Vehicle Routing with LKH3 Solver and Graph Classification with an Unsupervised Neural Embedding Framework
Spring 2018
Vinay K Mehta
Performance Evaluation of Open-Source RISC-V Cores
Fall 2017
Vishakh Balakuntalam Visweswara
Testing of Cache Coherence over the NoC
Saurabh Pradeep Bondarde
Cache Coherence over the NoC based on the TileLink Cache Coherence Support
Fall 2016
Marco Geuna
Integrating Complex Digital Systems: a RISC-V Based Open-Source Heterogeneous SoC