Education

University of Bologna, School of Math., Phys. and Nat. Sciences 2005 - 2008
Ph.D. in Computer Science Sponsored by ST Microelectronics Bologna - Italy
  • Thesis Design and Performance Evaluation of Network-on-Chip (NoC) Communication Protocols and Architectures.
  • Mentored 4 master students and collaborated with three international research labs.
  • Taught the OMNeT++ simulation framework at the Simulation master class.
Universite ́ Paris VII Denis Diderot 2003 - 2004
Stay-Abroad Study, funded by Erasmus scholarship Paris - France
  • Followed master classes
  • Learned French
University of Bologna, School of Math., Phys. and Nat. Sciences 1999 - 2005
Master and Bachelor degrees in Computer Science Bologna - Italy
  • Master Thesis Project and Analysis of Architectures and Protocols for NoCs. Final mark 110/110 summa cum laude

Research Experience

Columbia University, Department of Computer Science 2009 - present
Post-Doctoral Research Scientist at SLD research lab New York - USA
  • System-level design (OMNeT++ and SystemC TLM) of power-efficient NoC for multi-core Systems-on-Chip
  • Managed multiple research projects and teams of two to three researchers and students
  • Reviewer for Ieee TCAD, IET and ETRI journals, the DAC and NoCs conferences.
Columbia University, Department of Computer Science 2007 - 2009
Staff Research Associate at SLD research lab New York - USA
  • Proposed, and developed two system-level protocols to solve the message-dependent deadlock and time-closure exceptions in heterogeneous multi-core Systems-on-Chip

Professional Expericence

ST Microelectronics Advanced System Technology Lab. Summer 2004
Internship Grenoble - France
  • Developed a C++/OMNeT++ simulator to study the characteristics of the STM Spidergon NoC prototype.