Hardware Support for Synchronization

Intel 80x86:

Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual: "LOCK" instruction, which is basically implemented as a prefix byte to a subsequent instruction, which can be used to insure atomic access in a multiprocessor environment. Typically, it is used with "BTS" instruction, which is bit-test-and-set.

There is a note (p. 3-273), indicating that with Pentium Pro and beyond, that LOCK is not always necessary. Instead, just need to insure that an individual processor's cache is locked, using a cache coherency mechanism.

SPARC:

SWAP instruction, see SPARC IIe (Section 8.3.3)

M68000:

See John F. Wakerly, Microcomputer Architecture and Programming: the 68000 Family, John Wiley and Sons, New York, NY (1989), p. 422ff.

MIPS:

From MIPS IV Instruction Set, rev 3.2:

"There are paired instructions, Load Linked and Store Conditional, that can be used to perform atomic read-modify-write of word and doubleword cached memory locations. These instructions are used in carefully coded sequences to provide one of several synchronization primitives, including test-and-set, bit-level locks, semaphores, and sequencers/event counts."

E.g., LL: load linked word; SC: store conditional word; LD load linked doubleword; SCD store conditional doubleword