# PIN MAP for core < hps_sdram_p0 >
#
# Generated by hps_sdram_p0_pin_assignments.tcl
#
# This file is for reference only and is not used by Quartus Prime
#

INSTANCE: The_System|hps_0|hps_io|border|hps_sdram_inst
DQS: {HPS_DDR3_DQS_P[0]}
DQSn: {HPS_DDR3_DQS_N[0]}
DQ: {{HPS_DDR3_DQ[0]} {HPS_DDR3_DQ[1]} {HPS_DDR3_DQ[2]} {HPS_DDR3_DQ[3]} {HPS_DDR3_DQ[4]} {HPS_DDR3_DQ[5]} {HPS_DDR3_DQ[6]} {HPS_DDR3_DQ[7]}}
DM {HPS_DDR3_DM[0]}
CK: HPS_DDR3_CK_P
CKn: HPS_DDR3_CK_N
ADD: {HPS_DDR3_ADDR[0]} {HPS_DDR3_ADDR[10]} {HPS_DDR3_ADDR[11]} {HPS_DDR3_ADDR[12]} {HPS_DDR3_ADDR[1]} {HPS_DDR3_ADDR[2]} {HPS_DDR3_ADDR[3]} {HPS_DDR3_ADDR[4]} {HPS_DDR3_ADDR[5]} {HPS_DDR3_ADDR[6]} {HPS_DDR3_ADDR[7]} {HPS_DDR3_ADDR[8]} {HPS_DDR3_ADDR[9]}
CMD: HPS_DDR3_CAS_N HPS_DDR3_CKE HPS_DDR3_CS_N HPS_DDR3_ODT HPS_DDR3_RAS_N HPS_DDR3_WE_N
RESET: HPS_DDR3_RESET_N
BA: {HPS_DDR3_BA[0]} {HPS_DDR3_BA[1]} {HPS_DDR3_BA[2]}
PLL CK: cnn_hps_system:The_System|cnn_hps_system_hps_0:hps_0|cnn_hps_system_hps_0_hps_io:hps_io|cnn_hps_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
PLL DQ WRITE: cnn_hps_system:The_System|cnn_hps_system_hps_0:hps_0|cnn_hps_system_hps_0_hps_io:hps_io|cnn_hps_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk
PLL WRITE: cnn_hps_system:The_System|cnn_hps_system_hps_0:hps_0|cnn_hps_system_hps_0_hps_io:hps_io|cnn_hps_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
PLL DRIVER CORE: _UNDEFINED_PIN_
DQS_IN_CLOCK DQS_PIN (0): HPS_DDR3_DQS_P[0]
DQS_IN_CLOCK DQS_SHIFTED_PIN (0): The_System|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (0): The_System|hps_0|hps_io|border|hps_sdram_inst|div_clock_0
DQS_IN_CLOCK DIV_PIN (0): The_System|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]
DQS_OUT_CLOCK SRC (0): The_System|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (0): HPS_DDR3_DQS_P[0]
DQS_OUT_CLOCK DM (0): HPS_DDR3_DM[0]
DQSN_OUT_CLOCK SRC (0): The_System|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (0): HPS_DDR3_DQS_N[0]
DQSN_OUT_CLOCK DM (0): HPS_DDR3_DM[0]
READ CAPTURE DDIO: {*:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}
AFI RESET REGISTERS: *:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
SYNCHRONIZERS: *:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
SYNCHRONIZATION FIFO WRITE REGISTERS: *:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF*
SYNCHRONIZATION FIFO READ REGISTERS: *:The_System|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*]

#
# END OF INSTANCE: The_System|hps_0|hps_io|border|hps_sdram_inst

