QSYS = fpga/cnn_hps_system.qsys
SOPCINFO = fpga/cnn_hps_system.sopcinfo
QIP = fpga/cnn_hps_system/synthesis/cnn_hps_system.qip
HPS_PIN_TCL = fpga/cnn_hps_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl
HPS_PIN_MAP = hps_sdram_p0_all_pins.txt
QPF = cnn_process.qpf
QSF = cnn_process.qsf
SDC = cnn_process.sdc

DTS = $(SYSTEM).dts
DTB = $(SYSTEM).dtb

SOF = build/cnn_process.sof
RBF = build/soc_system.rbf


# qsys
#
# From the .qsys file, generate the .sopcinfo, .qip, and directory
# (named according to the system) with all the Verilog files, etc.

.PHONY : qsys
qsys : $(SOPCINFO)

$(SOPCINFO) $(QIP) $(HPS_PIN_TCL) $(SYSTEM)/ $(PRELOADER_SETTINGS_DIR) : $(QSYS)
	rm -rf $(SOPCINFO) $(SYSTEM)/
	qsys-generate $(QSYS) --synthesis=VERILOG

# quartus
#
# Run Quartus on the Qsys-generated files
#
#    Build netlist
# quartus_map soc_system
#
#    Use netlist information to determine HPS stuff
# quartus_sta -t hps_sdram_p0_pin_assignments.tcl soc_system
#
#    Do the rest
#   FIXME: this is wasteful.  Really want not to repeat the "map" step
# quartus_sh --flow compile 
#
# quartus_fit
# quartus_asm
# quartus_sta

.PHONY : quartus
quartus :
	quartus_map cnn_process
	quartus_fit cnn_process
	quartus_asm cnn_process

# rbf
#
# Convert the .sof file (for programming through the USB blaster)
# to an .rbf file to be placed on an SD card and written by u-boot
.PHONY : rbf
rbf :
	quartus_cpf -c $(SOF) $(RBF)
	@echo "scp $(RBF) root@IP:\"/mnt\""
