Function of different file for FPGA part:

command_receiver.sv:
Receive the command from HPS part which contain weight address, bias address, input feature address, input size, output size, convolution layer number, convolution state machine enable signal, input channel and output channel.

conv_state.sv:
Main state machine which used to control FPGA part caculation according to received message from software, it starts the DMA to load data and start caculate data and then transfer data out to sdram again.

dma_state_machine.sv:
DMA control state machine which used to receive command from upper level and start tranfer data from read address to write address by given message.

controller.sv:
Controller part top file, it is used as the top level for controller part.

s16_to_p1024.sv:
Transfer data from 16 bits to 1024 bits into input onchip memory in that DMA controller only has 16 bits datawidth while onchip memory need 1024 bits bandwidth.

mac_2.sv:
Multiply and addition caculation part to solve the convolution math problem.

pe_array.sv:
Instance the mac_2c.sv and generate 64 mac units to parallel caculate the data.

onchip_read_master_input.sv
Transfer data from onchip input memory into PE caculation part.

onchip_read_master_weight.sv:
Transfer data from onchip weight memory into PE caculation part.

p1024tos16.sv:
Transfer data from 1024 bits to 16 bits into output memory so that it could be arranged well.

pe_array_top.sv:
The top level file which contain pe_array.sv, onchip_read_master_input.sv, onchip_read_master_weight.sv, p1024tos16.sv and s16_to_p1024.sv

soc_system_top.sv:
The upper top level for project.