ADDRESS_ACLR_B=NONE
ADDRESS_REG_B=CLOCK0
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INTENDED_DEVICE_FAMILY="Cyclone V"
LPM_TYPE=altsyncram
NUMWORDS_A=8192
NUMWORDS_B=8192
OPERATION_MODE=DUAL_PORT
OUTDATA_ACLR_B=NONE
OUTDATA_REG_B=CLOCK0
POWER_UP_UNINITIALIZED=FALSE
RDCONTROL_REG_B=CLOCK0
READ_DURING_WRITE_MODE_MIXED_PORTS=OLD_DATA
WIDTHAD_A=13
WIDTHAD_B=13
WIDTH_A=32
WIDTH_B=32
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone V"
address_a
address_b
clock0
data_a
rden_b
wren_a
q_b
