commit 9cbd68476bd8045e95e91276e283cbf7532033a8
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed May 11 03:26:54 2016 -0400

    Working version of Chip8 EMulator

commit 4cb0402e07bc27139bb2ec94ed30b98be097cab5
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed May 11 02:34:55 2016 -0400

    Added double buffering

commit 10e88a207f36cec3a484a047409808596004284c
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed May 11 00:35:08 2016 -0400

    Added +2 to stack when popping

commit 98026152ae7b99b62a3af3b9d7f37b16bcb71472
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue May 10 22:14:00 2016 -0400

    Theoretical fix for infinite keypress waiting.

commit 680448658b65edfc694ef473da867d2d05be4fb3
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 22:00:27 2016 -0400

    Added stuff

commit b215d0325e08dff2d67519b258eb21cde202e898
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 20:44:38 2016 -0400

    Added correct PC_writedata case

commit 14fa0ec84b11bb1fcb3713d59a511428a3d529bf
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 20:42:43 2016 -0400

    Fixed enums

commit 1778fa04cc1ef9eedb8309aca2de91de227fa9c7
Merge: 1647c31 1b9a333
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 20:36:59 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 1647c3141e4ed1cff44e8e7af2a0f07106b7bd5f
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 20:36:37 2016 -0400

    Added new changes to software

commit 1b9a333ffde12cf77340a763c1c69e3d6635252b
Merge: 6be3433 9aafb45
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue May 10 20:33:28 2016 -0400

    Revamped CPU and Top after memory file findings. Pushing representative stack testbench.

commit 6be34339a828d7f32c80dc684393dbceac509f50
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue May 10 20:27:00 2016 -0400

    Revamped CPU and some Top to fix with memory module. Adding representative stack testbench.

commit 9aafb4524c6b3e45f6acfe553fcd08cf8440b4c3
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 18:51:22 2016 -0400

    Added missing enums

commit b71d4db1b9469cad2e763d550fc0f46e0c6f8c8a
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 10 15:59:10 2016 -0400

    Added changed stuff

commit cc8bc08af9a933ca683d01b0b0b2fb45495490fa
Merge: e9f7318 e1cd8d1
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon May 9 20:19:39 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit e9f73189e4d6b106bb55e6d1d9112f23d9938ed0
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon May 9 20:19:20 2016 -0400

    Possible draw-sprite fix.

commit e1cd8d18d6439d85845f1f281d040a3163f5ccbd
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Mon May 9 18:43:23 2016 -0400

    added tests for 1 and 2, expanded a CPU instruction to accomodate stack

commit 67d9cb4db4bf466ad8e0c16fa2de5d1fcfaae741
Merge: d9eed9c 1bff01e
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Mon May 9 18:40:22 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 1bff01e901e62f68ec67f276c111c94e0b75a832
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon May 9 18:39:38 2016 -0400

    Updated big CPU testbench

commit 2b8da46248698d2952be6ae234e2613a03dccf1e
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon May 9 18:00:04 2016 -0400

    Took out multiplier in led emulator. Small fixes for mem writing in Chip8_Top.

commit d9eed9ce7aae3db22a66af52f19c133b49498317
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Mon May 9 16:31:30 2016 -0400

    updated 00EE in CPU, added that test to testbench.

commit 839b32f08ebb3730f0e67d8a08aa03fe228b03e9
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon May 9 15:36:28 2016 -0400

    Fixed simple typo. -_-

commit fc3d05aa7a2c74c29b18bb0b21b83751dcb6ea09
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 18:37:50 2016 -0400

    Bug fixes in CPU-Top memory request interface. Switched instrs Fx65/Fx55 so they're right.

commit 99deaae0b4539d29b3ceb3ebee0f390a14ac34e0
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 16:58:37 2016 -0400

    Ash found small bug in Dxyn mem-request pattern. Fixed.

commit d197eca1ba52494f9445ee34d2635c71a0e75b4b
Author: David Watkins <djw2146@columbia.edu>
Date:   Sun May 8 09:52:38 2016 -0400

    Chip8 now outputs characters

commit 0058cc0831b800947b6b85f8b80f4f563a5a086a
Merge: d8cc820 2e1e52c
Author: David Watkins <djw2146@columbia.edu>
Date:   Sun May 8 05:45:09 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit d8cc820ec98ee24a27b830187f76125895a1223d
Author: David Watkins <djw2146@columbia.edu>
Date:   Sun May 8 05:44:43 2016 -0400

    Changed top level files

commit 2e1e52cfba28bce7b60bbc84277c0de3e4d46dd8
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 05:40:44 2016 -0400

    Updated cpu big testbench to reflect Dxyn isDrawing flag.

commit 7aa045ae83ba86b0d7abdd8765947133d2055667
Author: David Watkins <djw2146@columbia.edu>
Date:   Sun May 8 05:28:17 2016 -0400

    Added isDrawing flag

commit 9f51f4a9b46295363cf6bf1519678000f014be25
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 04:59:58 2016 -0400

    Added a few testing instructions.

commit ac45ce0a7523b032def876b7aa6397256199528d
Merge: 77f28cb d94043e
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 02:54:36 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 77f28cb7988ed39885f5a3a29bfdda65e91636bd
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 02:52:11 2016 -0400

    Added big testbench for CPU. Tested Dxyn draw-sprite::it works.

commit d94043ea52b16bf74ec6d5514691f516681d9008
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Sun May 8 02:19:05 2016 -0400

    added a cpu fix and tests for instructions 3-5 and 9-E (inclusive)

commit fa9819b7a998b5ff092a984cde2e2ba2132659d3
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Sun May 8 01:16:38 2016 -0400

    8-series cpu testbench + alu fix

commit 89203c16085cd8708c700188b375b7d85808d485
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 01:02:16 2016 -0400

    Cleaned up Dxyn draw sprite cmd. Still untested.

commit d5049e1a6185356d3af2f74076267fd49ebb99eb
Merge: 85cd6a8 22030b6
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 00:56:13 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 85cd6a80b1e954573d7fa240c019834ef1b7b828
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun May 8 00:54:43 2016 -0400

    Changed how draw-sprite-command Dxyn works. Untested.

commit 22030b63e776204af143883c4f288e194c65b43d
Author: David Watkins <djw2146@columbia.edu>
Date:   Sun May 8 00:09:25 2016 -0400

    Added proper key reading

commit fe2f4e96b21c6db9acc523832381fa6d227c44c2
Merge: 85e2d54 d63d5cb
Author: David Watkins <djw2146@columbia.edu>
Date:   Sat May 7 21:49:22 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 85e2d54f55d3a089d181bc78796ff2ba45c787f1
Author: David Watkins <djw2146@columbia.edu>
Date:   Sat May 7 21:49:02 2016 -0400

    Added reading and writing proper functionality

commit d63d5cb3591f7d481d0920abe76425f3113bc6db
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Sat May 7 19:43:33 2016 -0400

    basic framebuffer testbench w/rudimentary reset

commit e676f44becd5e6dd449422d014e027b4f064f495
Author: David Watkins <djw2146@columbia.edu>
Date:   Sat May 7 00:29:51 2016 -0400

    Added change to ispressed

commit 25466202fab00ebc180bc529d0163dea458b7b95
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sat May 7 00:27:30 2016 -0400

    Properly addressed enums.svh.

commit 6e7ee698ebe3ef5588029f59c26d14b95288ba3a
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sat May 7 00:15:20 2016 -0400

    Forgot to push CPU.

commit cc7eb43fac64d27a259030851aa15aee4e854f10
Merge: e7e44fb ad62fb7
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sat May 7 00:13:11 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit e7e44fb5c1a6e543d3bce3a76a5e4a724b3d13b9
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sat May 7 00:12:43 2016 -0400

    Added stack in. Updated top-level to reflect I/O changes. Prepping for compile.

commit ad62fb76fe236d96018b981edbd80b1485dcb98e
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Fri May 6 22:43:38 2016 -0400

    moved some declarations so it works

commit 965d008c4f4b735c9c4c44989aca249a425112bd
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Fri May 6 22:20:59 2016 -0400

    updated stack stuff

commit 6ef322275e702af5f30edd9aacee10c5e494838f
Author: gabriellet <gat2118@columbia.edu>
Date:   Fri May 6 21:00:32 2016 -0400

    stack testbench updated, stack passes tests

commit 858effa51dc45c746a19a737d797821fdc020183
Merge: ec6a883 960f694
Author: gabriellet <gat2118@columbia.edu>
Date:   Fri May 6 20:04:56 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit ec6a8838916b47857443fde5bcd9191ed1a49f27
Author: gabriellet <gat2118@columbia.edu>
Date:   Fri May 6 20:04:28 2016 -0400

    Stack testbench update

commit 960f6947b523d1a2c36a6aef02f214852aa27076
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 19:39:13 2016 -0400

    Added changes to makefile

commit 94932c1591f2e6bdcf5560a5600adb5e254749b6
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 14:21:14 2016 -0400

    Added changes to chip8_top

commit cdcfb9ff9fdecfc322e74b0b71f7db80ea6536eb
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 14:17:36 2016 -0400

    Added changes to stack to allow for multiple states

commit ff1990098338ff401861a4bd34074ebe104ea68f
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 13:21:28 2016 -0400

    Added compiling version of the driver

commit c7dd59eb78938c38f87a938f33492d28417971eb
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 03:27:37 2016 -0400

    Added skeleton code for new stack ops

commit 5a709b0648979746203101f37ad921df79a42c5a
Author: David Watkins <djw2146@columbia.edu>
Date:   Fri May 6 03:26:41 2016 -0400

    Added Stack operations

commit 30e93e3845b365ce2722ca3011e4d71d6925a89c
Merge: c5845b6 4baf65a
Author: David Watkins <djw2146@columbia.edu>
Date:   Thu May 5 02:48:03 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit c5845b6ca4bc6a12674a44a4f5ffb29fe53e560a
Author: David Watkins <djw2146@columbia.edu>
Date:   Thu May 5 02:47:24 2016 -0400

    Added bash file that can run modelsim from command line

commit 4baf65abbe6e1da8dbe6479f7c47de365c859bd1
Author: lpo2105 <lpo2105@micro6.ilab.columbia.edu>
Date:   Thu May 5 01:43:37 2016 -0400

    Added greater depth to testing approach.

commit 9f67225ddcb4bb9b0aa54204c612d6d1def0cdd8
Author: lpo2105 <lpo2105@micro6.ilab.columbia.edu>
Date:   Thu May 5 00:48:24 2016 -0400

    Adding CPU testbench for 6xkk/7xkk. Template to be extended to most CPU cmds.

commit d47c1b3833026dffca2c7fd54dc3783989e3bbc6
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 3 17:24:08 2016 -0400

    Removed "Hello world"

commit 83bd4ce83c55a21172903bd2cbc6ead0f6e4077a
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 3 17:23:08 2016 -0400

    All tests pass

commit 761072efe624954cf5cfa0438fc8b8d2c18a632f
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 3 16:48:15 2016 -0400

    Added testbench update

commit a79a5420cbbaf24d86f84b92bfcf4a2aaf0627c7
Merge: 35dfb69 53d84f5
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 3 16:14:01 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 53d84f54d5b3051834b034ad32f0cf4f930347d7
Merge: 22fe90c ed8e36c
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Tue May 3 15:26:36 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 22fe90c4e442c5e6dee85b7eda89162f04ff6303
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Tue May 3 15:26:03 2016 -0400

    cleaned up stack testbench

commit ed8e36c7356e3f099418e2888de466e1d0eac4d9
Merge: 719a978 cf347a1
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 15:14:54 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 719a978d4fcd00790ce49149ca0e4f075afddfc4
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 15:14:28 2016 -0400

    fb testbench update

commit cf347a195fa9023bc25c12e8f7a241f1549d48cb
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Tue May 3 15:05:38 2016 -0400

    Stack working. When reading, output will be available on second clock cycle. When enable = 00, it will read the value at the 0th place in the stack, ignore this.

commit cb46529016f72bf7410f10404df9fedf762b614f
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 13:39:19 2016 -0400

    tested ALU update

commit 87816742da290e4f79ade8934a370eed163c8f3d
Merge: 5a914f3 36e18d2
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 13:37:37 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 5a914f300ad9a6a9580cf4ad60c51deba4863ffd
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 13:37:15 2016 -0400

    updated tested ALU and enum

commit 35dfb697a5c5c9c4f7c483846fc381ade5bfb5f0
Merge: 4165b3d 36e18d2
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue May 3 13:33:03 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 36e18d283f432890f757638157050543925e3419
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Tue May 3 13:26:56 2016 -0400

    Update .gitignore

commit 1c7e5013d058406d0db3dc80bb155ca6892206ee
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Tue May 3 13:22:56 2016 -0400

    Fixed carry in ALU_f_ADD

commit 95b7b78a1768822c00fd4a3ef263b7bafde03535
Author: gabriellet <gat2118@columbia.edu>
Date:   Tue May 3 13:11:33 2016 -0400

    final ALU files - confirmed working

commit 8275d351c7b51571213c949e39a756ebf58a140f
Author: gabriellet <gat2118@columbia.edu>
Date:   Sat Apr 30 23:34:40 2016 -0400

    Stack testbench intermediate files:

commit 4c40781ff01ebe970ed4869a15cacf2832de7037
Author: gabriellet <gat2118@columbia.edu>
Date:   Sat Apr 30 23:32:19 2016 -0400

    ALU testbench files updated

commit 7ed35963899dce144ed4292b45bb16eed78d9ce0
Author: gabriellet <gat2118@columbia.edu>
Date:   Sat Apr 30 17:21:20 2016 -0400

    additional ALU test files

commit c6faa7efd3dc2d29ffaea21853acd405822b76f7
Author: gabriellet <gat2118@columbia.edu>
Date:   Sat Apr 30 17:19:56 2016 -0400

    ALU testing underway, still buggy

commit 2eab7a62d7b455e38b324c723b461ec29e0c6d53
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 16:06:36 2016 -0400

    new testbench files

commit e4f8c1ef00d2144481f1f63f74faa7a4c06e643f
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 15:49:32 2016 -0400

    moved audio files in test to test/audio

commit 529cdcfb17e518f53d2c7b88caffa99ce6b3b1e6
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 15:45:20 2016 -0400

    push stack ram to test/stk

commit e19c5f02d734e5572249e492e79890ea1f8c978c
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 13:32:43 2016 -0400

    stack testbench update

commit e5998b9b50fadeecafb85a5abd9697b598b21bb2
Merge: 9a46db3 0b17dc7
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 13:14:19 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog
    Stack updated, merging to testbench

commit 9a46db322947f85a19d149a3fc9fdcfff0dbaaa6
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 13:13:56 2016 -0400

    stack_testbench update

commit 0b17dc7a2c1ce76f303790bab864614746189dba
Merge: 3ac5cff 6ddb751
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Thu Apr 28 13:04:17 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 3ac5cfffa9b0ca446599d195381851d777b5cf4f
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Thu Apr 28 13:04:04 2016 -0400

    updated stack

commit 6ddb751b3ba98f4cf5a06c6f36ae5ccd3704771a
Author: gabriellet <gat2118@columbia.edu>
Date:   Thu Apr 28 12:51:14 2016 -0400

    Stack testbench files

commit 889fbe39b2d2a638312fe15fdb16b5a94c2414ef
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Apr 28 00:09:17 2016 -0400

    Revamped framebuffer and CPU to match. Theoretically supports draw sprite and clear screen cmds. CHANGES NOT REFLECTED IN Chip8_Top

commit 18e996d09a296988bfc56018fc85abce34341a2a
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Wed Apr 27 18:17:44 2016 -0400

    Adding MegaFunction Framebuffer memory.

commit 2913ad5cfc62beb48050c2705d375b981103d3d3
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue Apr 26 21:55:28 2016 -0400

    Fixed CPU casex-ladder syntax problems for DC conditions. Cleaned up truncation warnings. Tested triple-ported-register-file. It seems to work.

commit 4165b3d491665156e77feb45618226961df4cdff
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 14:52:57 2016 -0400

    Added a python script for generating properly formatted MIF files

commit 5e6485faef80c816c1ad30c4b84635552b2e4b04
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 08:07:17 2016 -0400

    Updated code to support instructions at top level

commit dfd8770b0b2b77dca4b54fcedbc0f806b6e0ac87
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 06:57:58 2016 -0400

    Compiling version of entire project

commit 932855dd20090b7ad68be05b9c9009ae2d762ec2
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 04:14:34 2016 -0400

    Added updates to the sound controller

commit aa6f9247e0d2766b790dfafb3c8520e32ca3081b
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 03:46:59 2016 -0400

    Added header files

commit 7f698e00b0b09c2348541596c9b71568eb5bf98e
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 26 03:38:25 2016 -0400

    Fixed ALU and CPU to support all instruction (Draw NYI)

commit 2a1286c317fd71e37bfe17bb83903c56bb340d27
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Mon Apr 25 01:34:59 2016 -0400

    Added most PC functionality to the CPU.

commit 0ddddfb9e4ef23b12aa804610d08ce9819a9ddde
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun Apr 24 23:55:18 2016 -0400

    Added BCD functionality to CPU. Fixed oversized default value in random num generator.

commit b58aa9ef625b711d4180fedc31c5ce193eccb036
Merge: 9cbc6d7 3de4899
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun Apr 24 23:40:36 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 9cbc6d726f251f8ef79a779751bd8a60dc902c99
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun Apr 24 23:39:50 2016 -0400

    Updated CPU for top-level control. It does not deal with instrs regarding PC, framebuffer, or BCD.

commit 3de48994fb16a1fa8d2e4952da22f1527fe5153b
Author: ask2203 <ask2203@micro15.ilab.columbia.edu>
Date:   Sat Apr 23 18:13:12 2016 -0400

    untested stack file

commit b172666ea7b2de978e5c5096882a788f4a0ea9a6
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:22:09 2016 -0400

    Duplicated files deleted

commit 2d0c61a7e144c8759127d99af262cbd7c1140d64
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:21:28 2016 -0400

    Duplicated files deleted

commit 34e241302a4ef0977bbdbe2e5394f0dc8f6556b6
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:21:08 2016 -0400

    Duplicated files deleted

commit f0a1dc7c772ed001e2073d755dd7f1d67ce37547
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:20:58 2016 -0400

    Duplicated files deleted

commit d56f6ab9c26e0d9fd880f727d6be6fbbec44be6e
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:20:47 2016 -0400

    Duplicated files deleted

commit 92890f725928acce4d7755c0784d69cca85062ac
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:20:34 2016 -0400

    Duplicated files deleted

commit be03d04f33b42f09ee3dfb45c2b5cd0cf547df4e
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Fri Apr 22 18:17:14 2016 -0400

    Script + samples + original wav
    
    Script extracts samples from wav file. Samples for beep2.wav are in samples.txt

commit b705539fb6021353ac2ddb476142288cf3f267a1
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 19 15:51:50 2016 -0400

    Added files that wer emissing from before

commit 512823e2a46d09a3d8305699f60615b0a0988908
Author: David Watkins <djw2146@columbia.edu>
Date:   Sat Apr 16 18:11:21 2016 -0400

    Moved testbench for delay timer

commit 844880913d18dee6e4c4cee38dd8a12c012a413f
Author: David Watkins <djw2146@columbia.edu>
Date:   Sat Apr 16 18:08:35 2016 -0400

    Redid file directory

commit f55eb911738c27765f9c0a8f8158ba6393cd541b
Author: gabriellet <gat2118@columbia.edu>
Date:   Sat Apr 16 07:24:54 2016 -0400

    removed mips directory from test, added delay timer and testbench to test

commit ef7706c9c01f65935ec1f8d8ba75900d9821b824
Merge: 6e306a2 fcb610e
Author: gabriellet <gat2118@columbia.edu>
Date:   Fri Apr 15 12:22:42 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 6e306a29a061cb4612c4e1c4c6160b731e7ec84a
Author: gabriellet <gat2118@columbia.edu>
Date:   Fri Apr 15 12:21:58 2016 -0400

    delay timer implementation

commit fcb610e9bfb6face733099142e3a1d275106f871
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Wed Apr 13 23:50:14 2016 -0400

    Here is the test waveform to show on Thursday Apr 14. I am the prettiest.

commit fa449ed041a88e713c1f133beb3033e2a5f48021
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 23:02:56 2016 -0400

    Forgot test

commit 050daf1090a867f8181af4f1db6bbaad9c6054f6
Merge: c37a15a ac284ac
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 22:46:39 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit c37a15a2e2f3ffd0e0ccdb502336571f20f50000
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 22:46:23 2016 -0400

    Cries

commit ac284ac58a27087d4766eb4ccd0061ee9e555917
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Wed Apr 13 22:40:15 2016 -0400

    Added dual ported memory for register file and memory.

commit 07694cbe2ac21b44c806dc56c466470b44dfdc02
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 22:30:14 2016 -0400

    Added testbench

commit ade90c0e38478bbeb1ccd93f255fce8834adf321
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 22:03:12 2016 -0400

    Added test rom initialization file that tests basic instructions

commit 0e31d27cf7e437b01e5e055bb7d90e229c0de5db
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 21:56:58 2016 -0400

    Added a new top level module that runs over the pc

commit 2133d107428c3ad7ad74065bca527d4e7fb1f2a4
Merge: 77d791d 1443ecb
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 21:31:27 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit 77d791dc6a4f63a5a0ea4fecd13c111f1d2d1700
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Apr 13 21:31:10 2016 -0400

    Added in progress version of chip8 top level

commit 1443ecb60c1d37b41f097d38155e532bc3c2d5c0
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Wed Apr 13 20:42:55 2016 -0400

    fixed dec-hex

commit 4ffe66bcffed6e9a54b3c44b7111ea0428327a8f
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Wed Apr 13 19:02:48 2016 -0400

    Delete SoCKit_Top.ipinfo

commit dbbdc521e65452464f9d20f66fe9b73828dac53a
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Wed Apr 13 19:02:43 2016 -0400

    Delete SoCKit_Top.sld_design_entry.sci

commit 4c5ce1ca7dd6541308ef7f923505f80bb075035f
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Wed Apr 13 19:02:38 2016 -0400

    Delete SoCKit_Top.db_info

commit 966343eeb5429e8624554017bb7ac7ba6e62a27c
Author: gat2118 <gat2118@micro18.ilab.columbia.edu>
Date:   Wed Apr 13 16:37:06 2016 -0400

    copied files to test in order to implement MIPS-like processor design

commit 6c913287ef3c20a539423cbe0cd6715d7f0a2923
Merge: 8048a4a a67a547
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Tue Apr 12 14:44:31 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit a67a547f37b38d65657e96f8174ba7acf63dfdef
Merge: af3718e 9761ee9
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 12 14:16:55 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit af3718ee4f5a685290f46ec466e8562c2d9711ed
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 12 14:16:27 2016 -0400

    Added register file code

commit 8048a4a57a22b65b5a41c11d1851bbe225e8145a
Author: Ashley Kling <ask2203@columbia.edu>
Date:   Tue Apr 12 13:57:34 2016 -0400

    updated CPU file, need to test, esp # cycles per instruction

commit 9761ee95f0496f077c326bee4aba1825aeedd73f
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Tue Apr 12 13:48:02 2016 -0400

    Update README.md

commit 5cd366cfed3ea15b0c9961b5ca37ee9bf98cb840
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Tue Apr 12 12:19:30 2016 -0400

    Update README.md

commit 553cfe6250d772c230278d92c4ec80d0fc230a93
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Tue Apr 12 12:19:05 2016 -0400

    Update README.md

commit 02e3c4b657d98c03c53c3f1d7d5bc501ad851dc4
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 12 16:56:18 2016 +0100

    dded u-boot script which is necessary for getting the sockit board to boot

commit dd7d50a9e71b0c4f1623d25148c4d96b4790e306
Merge: b15ad94 f9f3232
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 12 03:58:11 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit b15ad94df32fd92cbf140653c3f5b44649d32daa
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Apr 12 03:57:31 2016 -0400

    Added communication back and forth. Needs testing

commit f9f3232503cc2a16efe751c24054502fc8ed20c8
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Mon Apr 11 14:29:13 2016 -0400

    Update sockit_top.sv

commit 5ca73ee5a326b6b758c9046ed2cab6b02ed9aa6c
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Mon Apr 11 14:15:56 2016 -0400

    Changed implementation
    
    Clock is now default low (no edge detection necessary for use in delay, sound timers).

commit 99ac7117f1e962f780f1ff26d8026510292eec02
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Mon Apr 11 12:55:44 2016 -0400

    clk_div.sv works
    
    Seems to work in simulation. Will try a few more tests with edge cases to determine behavior.

commit 75aa22faed1b3fabc1f3439d8df2defcded46e95
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Mon Apr 11 12:28:07 2016 -0400

    bcd.sv now works
    
    Tests indicate module works.

commit a744ba2ec0ca570e06cecc2770aedd176d044d2d
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sun Apr 10 13:30:36 2016 -0400

    Fix compilation errors
    
    Simulated in modelsim but still does not work. Loop in line 13 only runs once. Will investigate why.

commit fd6b8e93cce11ec12061d7a328f912fbe85f1cad
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun Apr 10 03:32:07 2016 -0400

    Adding memory module waveform test.

commit 4b5e6b9b12c7e6706af463a5324b2b65ba1626cb
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Sun Apr 10 03:18:46 2016 -0400

    Added 4096byte memory module.

commit 90fd2f67f770b0eb25a8930198fbd8b05b8afa88
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:52:47 2016 -0400

    BCD module in systemverilog

commit 6de8348fd274c49e7564113fcf631f53b4cbfc32
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:24:38 2016 -0400

    Information relevant to audio test

commit df18feae1c60ffe03b53e1bf4117c52852969b2b
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:19:38 2016 -0400

    Rename sockit_top.sv to test/sockit_top.sv

commit 08b5170a0a56c9c93b32fbd4386313c09af62bc2
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:19:18 2016 -0400

    Rename i2c_controller.sv to test/i2c_controller.sv

commit f8d101603af378f5a6d530a1a924ba3a05a383e9
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:19:06 2016 -0400

    Rename i2c_av_config.sv to test/i2c_av_config.sv

commit 2566be1a0a3a9cc017a8ba3829e0894e12fbd3ff
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:18:50 2016 -0400

    Rename delay_timer.sv to test/delay_timer.sv

commit 7a3c6f0788411ac69e24c6680e1104ed22a31167
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:18:37 2016 -0400

    Rename audio_effects.sv to test/audio_effects.sv

commit e4ebe895dc5205aaf655a51849df03bb5f08268c
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:18:17 2016 -0400

    Rename audio_codec.sv to test/audio_codec.sv

commit 070b16f32c9820b0c0d15aca5b321020e9d181fa
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:17:52 2016 -0400

    Test for SoCKit Sound
    
    Tests whether SoCKit board will output 440Hz sine wave

commit 1d325b6e8e083bfcd199f182fa298fa31fde876d
Author: Gabrielle A Taylor <gat2118@columbia.edu>
Date:   Sat Apr 9 22:12:39 2016 -0400

    Clock divider
    
    Converts from 50MHz clock to 60Hz clock. To be used in delay and sound timers.

commit 51f1409a2ae329f78aa28986d65e4fae7b306df0
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Apr 7 13:51:30 2016 -0400

    ACTUALLY added initial CPU vwf test.

commit 174d5f5228965d9067ab7cd326f82fb7ca7ba5d0
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Apr 7 13:49:56 2016 -0400

    Comb instr decode works. Cleaned code. Adding CPU vwf test.

commit 260a661a7c625be088986997ee5c417edda4ca01
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Apr 7 13:29:00 2016 -0400

    Made instruction decode combinational. I believe it works, but not all instrs implemented were tested.

commit 0da757bd8e26d569a3ee7682fbac164fe97339b8
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue Apr 5 23:58:29 2016 -0400

    Started CPU. Data is not appearing as expected. See CPU_initial_test.vwf waveform.

commit 146d5c3b0dcc7412d0853dc1258e1d5ab239a3a2
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Tue Apr 5 21:07:43 2016 -0400

    Created register module to control V0-VF. Also created a folder to hold test waveforms.

commit 904fba10987ee571bae75211cf3992935e10ec45
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Mar 31 02:54:44 2016 -0400

    Added 16b random number generator.

commit e3410e4fb4c763867bdb6e503751ed155e06830c
Author: lpo1234 <lpo1017@frontiernet.net>
Date:   Thu Mar 31 00:07:47 2016 -0400

    Added ALU and memory-to-screen VGA emulator

commit 9b629ea8e3d0dde730a90f39806208222fde5965
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Mar 30 16:12:46 2016 -0400

    Fixed key press values

commit 6520961eb44e7fb8d902c80adb6ce8c38807276c
Merge: ef35672 ad878f1
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Mar 30 04:03:29 2016 -0400

    Merge branch 'master' of https://github.com/DavidWatkins/Chip8-SystemVerilog

commit ef35672328ff42b0b4fcde7d7391555aaa3574da
Author: David Watkins <djw2146@columbia.edu>
Date:   Wed Mar 30 04:02:55 2016 -0400

    New status for stuff. Added a bunch of local stuff

commit ad878f13b861ec9b4084a9eaf8d94309be5f1590
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Tue Mar 29 23:50:36 2016 -0400

    Update Chip8_VGA_Emulator.sv

commit 7b43eb8ec84468304dbae5eba2a739278eb2fc16
Author: David Watkins <djw2146@columbia.edu>
Date:   Tue Mar 29 23:34:08 2016 -0400

    Added changes to framebuffer code

commit cab0f99bfc540cd1a64a27a29ba18d5c68818b32
Author: David Watkins <djw2146@columbia.edu>
Date:   Mon Mar 28 23:34:20 2016 -0400

    Initial commit

commit 7e436e72239b592fb76c50e6d126497341210cea
Author: David Watkins <DavidWatkins@users.noreply.github.com>
Date:   Mon Mar 28 17:23:05 2016 -0400

    Initial commit
