Altera SOPC Builder Version 9.10 Build 222
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved.


No .sopc_builder configuration file(!)
# 2015.08.06 14:00:11 (*) mk_custom_sdk starting
# 2015.08.06 14:00:11 (*) Reading project G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0.ptf.

# 2015.08.06 14:00:11 (*) Finding all CPUs
# 2015.08.06 14:00:11 (*) Finding all available components
# 2015.08.06 14:00:11 (*) Reading G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/.sopc_builder/install.ptf

# 2015.08.06 14:00:11 (*) Found 70 components

# 2015.08.06 14:00:11 (*) Finding all peripherals

# 2015.08.06 14:00:11 (*) Finding software components

# 2015.08.06 14:00:12 (*) (Legacy SDK Generation Skipped)
# 2015.08.06 14:00:12 (*) (All TCL Script Generation Skipped)
# 2015.08.06 14:00:12 (*) (No Libraries Built)
# 2015.08.06 14:00:12 (*) (Contents Generation Skipped)
# 2015.08.06 14:00:12 (*) mk_custom_sdk finishing

# 2015.08.06 14:00:12 (*) Starting generation for system: system_0.

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# 2015.08.06 14:00:12 (*) Running Generator Program for cpu_0

# 2015.08.06 14:00:13 (*)   IP functional simulation model enabled: Uncheck System Generation Simulation box for faster generation if HDL Simulation not required.
# 2015.08.06 14:00:13 (*) Starting Nios II generation
# 2015.08.06 14:00:13 (*)   Checking for plaintext license.
# 2015.08.06 14:00:14 (*)   Couldn't query license setup in Quartus directory d:/altera/91/quartus
# 2015.08.06 14:00:14 (*)   Defaulting to contents of LM_LICENSE_FILE environment variable
# 2015.08.06 14:00:14 (*)   Plaintext license not found.

# 2015.08.06 14:00:14 (*)   Checking for encrypted license (non-evaluation).
# 2015.08.06 14:00:14 (*)   Couldn't query license setup in Quartus directory d:/altera/91/quartus
# 2015.08.06 14:00:14 (*)   Defaulting to contents of LM_LICENSE_FILE environment variable
# 2015.08.06 14:00:14 (*)   Encrypted license found.  SOF will not be time-limited.
# 2015.08.06 14:00:14 (*)   Getting CPU configuration settings
# 2015.08.06 14:00:14 (*)   Elaborating CPU configuration settings
# 2015.08.06 14:00:14 (*)   Creating all objects for CPU

# 2015.08.06 14:00:14 (*)     Testbench
# 2015.08.06 14:00:14 (*)     Instruction decoding
# 2015.08.06 14:00:14 (*)       Instruction fields
# 2015.08.06 14:00:14 (*)       Instruction decodes
# 2015.08.06 14:00:15 (*)       Signals for RTL simulation waveforms
# 2015.08.06 14:00:15 (*)       Instruction controls
# 2015.08.06 14:00:15 (*)     Pipeline frontend
# 2015.08.06 14:00:15 (*)     Pipeline backend
# 2015.08.06 14:00:17 (*)   Creating 'G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0_sim/cpu_0.do'

# 2015.08.06 14:00:17 (*)   Generating HDL from CPU objects
# 2015.08.06 14:00:18 (*)   Creating encrypted HDL
# 2015.08.06 14:00:19 (*)   Creating IP functional simulation model
# 2015.08.06 14:00:28 (*) Done Nios II generation

# 2015.08.06 14:00:28 (*) Running Generator Program for jtag_uart_0

# 2015.08.06 14:00:29 (*) Running Generator Program for uart_0

# 2015.08.06 14:00:30 (*) Running Generator Program for sram_0

# 2015.08.06 14:00:31 (*) Running Generator Program for epcs_controller

# 2015.08.06 14:00:32 (*) Running Generator Program for cfi_flash_0

# 2015.08.06 14:00:32 (*) Running Generator Program for sdram_0

# 2015.08.06 14:00:33 (*) Running Generator Program for LEDG

# 2015.08.06 14:00:34 (*) Running Generator Program for LEDR

# 2015.08.06 14:00:34 (*) Running Generator Program for KEY

# 2015.08.06 14:00:35 (*) Running Generator Program for Switch

# 2015.08.06 14:00:35 (*) Running Generator Program for SEG7

# 2015.08.06 14:00:36 (*) Running Generator Program for VGA

VGA Controller resolution has been set to 640x480
Ensure that vga_clk is connected to a 25MHz clock

# 2015.08.06 14:00:37 (*) Running Generator Program for PS2_CLK

# 2015.08.06 14:00:37 (*) Running Generator Program for PS2_DAT

# 2015.08.06 14:00:38 (*) Running Generator Program for BUZZER

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# 2015.08.06 14:00:38 (*) Running Test Generator Program for sdram_0

# 2015.08.06 14:00:39 (*) Making arbitration and system (top) modules.

# 2015.08.06 14:00:44 (*) Generating Quartus symbol for top level: system_0

# 2015.08.06 14:00:44 (*) Generating Symbol G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0.bsf

# 2015.08.06 14:00:44 (*) Creating command-line system-generation script: G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0_generation_script

# 2015.08.06 14:00:44 (*) Running setup for HDL simulator: modelsim


Building ModelSim Project

'vsim' ڲⲿҲǿеĳ
ļ

# 2015.08.06 14:00:44 (*) Completed generation for system: system_0.
# 2015.08.06 14:00:44 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0.ptf 
  System HDL Model : G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0.v 
  System Generation Script : G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0_generation_script 
  HDL Simulation Directory : G:/FPGA_PRJ/my_nios_729/vga_nios_729/DE1_NIOS/system_0_sim 

# 2015.08.06 14:00:44 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.
