BlazePPS_v2/hardware README

Valeh Valiollahpour Amiri (vv2252@columbia.edu)
Christopher Campbell (cc3769@columbia.edu)
Yuanpei Zhang (yz2727@columbia.edu)
Sheng Qian (sq2168@columbia.edu)

What is included:
Directories & Files
Opening Project
Compiling Project
Programming FPGA
Testing

--------------------
Directories & Files
--------------------

  - README
      You're reading me.

  - Makefile
      Used for opening the project, compiling the project, programming the FPGA, and
      testing the project.
 
  - SoCKit_top.sv
      Top level.

  - blazepps.qsys
      QSys design.

  - blazepps

      - synthesis

          - blazepps.v
              Qsys design module.

          + submodules
              Contains submodules for main Qsys design module (includes hps, clk_0,
              xaui_clk, master_0 (jtag), tx_oc_fifo, rx_oc_fifo, tx_dc_fifo, tx_dc_fifo, 
              10g_mac).

  + xaui
      Contains files for XAUI IP core.

  + pll
      Contains files for PLL IP core.

  - output_file
     
      - SoCKit_Top.sof
          The image of our compiled project, which can be used to directly program the
          FPGA or produce a .rbf file.

  - txbuffer.sv
      tx buffer mdoule (ensures the tx MAC gets 8 bytes of incoming data at a time).

  - loopback_test.tcl
      Tests tx->rx loopback (can be used with any of the tx->rx loopback modules).

  - rx_stream.tcl
      Tests rx (network->fpga);

  - syscon-test.tcl
      Tests JTAG chain.
 
  - tx_stream.tcl
      Tests tx (fpga->network).

  + test_packets
     Contains test packets (pcap files) for use with tx and rx tests 

----------------
Opening Project
----------------

$ make open

------------------
Compiling Project
------------------

$ make compile

-----------------
Programming FPGA
-----------------

$ make program

--------
Testing
--------

  - Starting JTAG processes

      $ make jtag

  - Launching System Console

      $ make syscon

  - Launching Wireshark

      $ make wireshark

  - TCP Dump (dumps incoming packets on eth4)

      $ make dump

  - TCP Replay (replays a single packet on eth4)

      $ make replay

  - Test Tx (send a packet from FPGA to network)

      $ make test_tx

  - Test Rx (send a packet from network to FPGA)
	
      $ make test_rx

  - Test loopback (send a packet from FPGA tx and expect it to loopback to FPGA rx)

      $ make test_lo
