# do SoCKit_Top_run_msim_rtl_vhdl.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying /opt/altera/quartus-13.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /opt/altera/quartus-13.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlib lab3
# ** Warning: (vlib-34) Library already exists at "lab3".
# vmap lab3 lab3
# Modifying modelsim.ini
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/lab3.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3
# 
# Top level modules:
# 	lab3
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_reset_controller.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_reset_controller
# 
# Top level modules:
# 	altera_reset_controller
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_reset_synchronizer.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_reset_synchronizer
# 
# Top level modules:
# 	altera_reset_synchronizer
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0
# 
# Top level modules:
# 	lab3_mm_interconnect_0
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_sc_fifo.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/miner_top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module miner_top
# 
# Top level modules:
# 	miner_top
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/fpgaminer_top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module fpgaminer_top
# 
# Top level modules:
# 	fpgaminer_top
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/sha256_transform.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module sha256_transform
# -- Compiling module sha256_digester
# 
# Top level modules:
# 	sha256_transform
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/sha-256-functions.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module e0
# -- Compiling module e1
# -- Compiling module ch
# -- Compiling module maj
# -- Compiling module s0
# -- Compiling module s1
# 
# Top level modules:
# 	e0
# 	e1
# 	ch
# 	maj
# 	s0
# 	s1
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_master_0.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_master_0
# 
# Top level modules:
# 	lab3_master_0
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_master_0_p2b_adapter.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_master_0_p2b_adapter
# 
# Top level modules:
# 	lab3_master_0_p2b_adapter
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_master_0_b2p_adapter.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_master_0_b2p_adapter
# 
# Top level modules:
# 	lab3_master_0_b2p_adapter
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_packets_to_master.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_packets_to_master
# -- Compiling module packets_to_fifo
# -- Compiling module fifo_buffer_single_clock_fifo
# -- Compiling module fifo_buffer_scfifo_with_controls
# -- Compiling module fifo_buffer
# -- Compiling module fifo_to_packet
# -- Compiling module packets_to_master
# 
# Top level modules:
# 	altera_avalon_packets_to_master
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_packets_to_bytes.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_packets_to_bytes
# 
# Top level modules:
# 	altera_avalon_st_packets_to_bytes
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_bytes_to_packets.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_bytes_to_packets
# 
# Top level modules:
# 	altera_avalon_st_bytes_to_packets
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_master_0_timing_adt.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_master_0_timing_adt
# 
# Top level modules:
# 	lab3_master_0_timing_adt
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_jtag_interface.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_jtag_interface
# 
# Top level modules:
# 	altera_avalon_st_jtag_interface
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_jtag_dc_streaming.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_jtag_control_signal_crosser
# -- Compiling module altera_jtag_src_crosser
# -- Compiling module altera_jtag_dc_streaming
# 
# Top level modules:
# 	altera_jtag_dc_streaming
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_jtag_sld_node.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_jtag_sld_node
# 
# Top level modules:
# 	altera_jtag_sld_node
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_jtag_streaming.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_jtag_streaming
# 
# Top level modules:
# 	altera_jtag_streaming
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_clock_crosser.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_clock_crosser
# 
# Top level modules:
# 	altera_avalon_st_clock_crosser
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_pipeline_base.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_pipeline_base
# 
# Top level modules:
# 	altera_avalon_st_pipeline_base
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_idle_remover.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_idle_remover
# 
# Top level modules:
# 	altera_avalon_st_idle_remover
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_avalon_st_idle_inserter.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_avalon_st_idle_inserter
# 
# Top level modules:
# 	altera_avalon_st_idle_inserter
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_hps_0.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_hps_0
# 
# Top level modules:
# 	lab3_hps_0
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_hps_0_hps_io.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_hps_0_hps_io
# 
# Top level modules:
# 	lab3_hps_0_hps_io
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram
# 
# Top level modules:
# 	hps_sdram
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_acv_hard_memphy
# 
# Top level modules:
# 	hps_sdram_p0_acv_hard_memphy
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_altdqdqs.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_altdqdqs
# 
# Top level modules:
# 	hps_sdram_p0_altdqdqs
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_acv_hard_addr_cmd_pads
# 
# Top level modules:
# 	hps_sdram_p0_acv_hard_addr_cmd_pads
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_clock_pair_generator
# 
# Top level modules:
# 	hps_sdram_p0_clock_pair_generator
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_generic_ddio.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_generic_ddio
# 
# Top level modules:
# 	hps_sdram_p0_generic_ddio
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_acv_hard_io_pads
# 
# Top level modules:
# 	hps_sdram_p0_acv_hard_io_pads
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0_acv_ldc.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0_acv_ldc
# 
# Top level modules:
# 	hps_sdram_p0_acv_ldc
# vlog -vlog01compat -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_mem_if_hhp_qseq_synth_top
# 
# Top level modules:
# 	altera_mem_if_hhp_qseq_synth_top
# vlog -vlog01compat -work work +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys {/home/user5/spring14/px2117/Desktop/lab3-qsys/SoCKit_top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module SoCKit_Top
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/SoCKit_top.v(585): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	SoCKit_Top
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_irq_mapper.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_irq_mapper
# 
# Top level modules:
# 	lab3_irq_mapper
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_width_adapter.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_width_adapter
# 
# Top level modules:
# 	altera_merlin_width_adapter
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_address_alignment.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_address_alignment
# 
# Top level modules:
# 	altera_merlin_address_alignment
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_burst_uncompressor.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_arbitrator.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_rsp_xbar_mux.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_rsp_xbar_mux
# 
# Top level modules:
# 	lab3_mm_interconnect_0_rsp_xbar_mux
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_rsp_xbar_demux.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_rsp_xbar_demux
# 
# Top level modules:
# 	lab3_mm_interconnect_0_rsp_xbar_demux
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_cmd_xbar_mux.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_cmd_xbar_mux
# 
# Top level modules:
# 	lab3_mm_interconnect_0_cmd_xbar_mux
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_cmd_xbar_demux.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_cmd_xbar_demux
# 
# Top level modules:
# 	lab3_mm_interconnect_0_cmd_xbar_demux
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_burst_adapter.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_burst_adapter_burstwrap_increment
# -- Compiling module altera_merlin_burst_adapter_adder
# -- Compiling module altera_merlin_burst_adapter_subtractor
# -- Compiling module altera_merlin_burst_adapter_min
# -- Compiling module altera_merlin_burst_adapter
# -- Compiling module altera_merlin_burst_adapter_uncompressed_only
# -- Compiling module altera_merlin_burst_adapter_full
# 
# Top level modules:
# 	altera_merlin_burst_adapter
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_id_router.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_id_router_default_decode
# -- Compiling module lab3_mm_interconnect_0_id_router
# 
# Top level modules:
# 	lab3_mm_interconnect_0_id_router
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_mm_interconnect_0_addr_router.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_mm_interconnect_0_addr_router_default_decode
# -- Compiling module lab3_mm_interconnect_0_addr_router
# 
# Top level modules:
# 	lab3_mm_interconnect_0_addr_router
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_slave_agent
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(591): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(472): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(473): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(474): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(475): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_agent.sv(34): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# 
# Top level modules:
# 	altera_merlin_slave_agent
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_master_agent.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_master_agent
# 
# Top level modules:
# 	altera_merlin_master_agent
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_axi_master_ni
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(748): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(752): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(686): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(688): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(690): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(692): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(707): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(723): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(725): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(727): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_axi_master_ni.sv(729): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# 
# Top level modules:
# 	altera_merlin_axi_master_ni
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_slave_translator.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_merlin_master_translator.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_mem_if_hard_memory_controller_top_cyclonev
# 
# Top level modules:
# 	altera_mem_if_hard_memory_controller_top_cyclonev
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_mem_if_oct_cyclonev.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_mem_if_oct_cyclonev
# 
# Top level modules:
# 	altera_mem_if_oct_cyclonev
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altera_mem_if_dll_cyclonev.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altera_mem_if_dll_cyclonev
# 
# Top level modules:
# 	altera_mem_if_dll_cyclonev
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module altdq_dqs2_acv_connect_to_hard_phy_cyclonev
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv(198): (vlog-2597) '4294967295' is being treated as 32-bit signed integer and will overflow.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv(2234): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv(2238): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv(2218): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# 
# Top level modules:
# 	altdq_dqs2_acv_connect_to_hard_phy_cyclonev
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_p0.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_p0
# 
# Top level modules:
# 	hps_sdram_p0
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/hps_sdram_pll.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module hps_sdram_pll
# 
# Top level modules:
# 	hps_sdram_pll
# vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_hps_0_hps_io_border.sv}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module lab3_hps_0_hps_io_border
# ** Error: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_hps_0_hps_io_border.sv(85): (vlog-2730) Undefined variable: 'intermediate'.
# ** Error: /home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules/lab3_hps_0_hps_io_border.sv(108): 'intermediate' already declared in this scope (lab3_hps_0_hps_io_border).
# ** Error: /opt/altera/quartus-13.1/modelsim_ase/linuxaloem/vlog failed.
# Error in macro ./SoCKit_Top_run_msim_rtl_vhdl.do line 69
# /opt/altera/quartus-13.1/modelsim_ase/linuxaloem/vlog failed.
#     while executing
# "vlog -sv -work lab3 +incdir+/home/user5/spring14/px2117/Desktop/lab3-qsys/lab3/synthesis/submodules {/home/user5/spring14/px2117/Desktop/lab3-qsys/lab..."
vsim work.SoCKit_Top
# vsim work.SoCKit_Top 
# Loading work.SoCKit_Top
# ** Error: (vsim-3033) /home/user5/spring14/px2117/Desktop/lab3-qsys/SoCKit_top.v(658): Instantiation of 'lab3' failed. The design unit was not found.
#         Region: /SoCKit_Top
#         Searched libraries:
#             /home/user5/spring14/px2117/Desktop/lab3-qsys/simulation/modelsim/rtl_work
# Error loading design
