Altera SOPC Builder Version 11.00 Build 157
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved.


No .sopc_builder configuration file(!)
# 2012.09.06 23:55:10 (*) mk_custom_sdk starting
# 2012.09.06 23:55:10 (*) Reading project C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU.ptf.

# 2012.09.06 23:55:10 (*) Finding all CPUs
# 2012.09.06 23:55:10 (*) Finding all available components
# 2012.09.06 23:55:10 (*) Reading C:/Users/Gardner/Desktop/tetris_0/lab3/.sopc_builder/install.ptf

# 2012.09.06 23:55:10 (*) Found 68 components

# 2012.09.06 23:55:11 (*) Finding all peripherals

# 2012.09.06 23:55:11 (*) Finding software components

# 2012.09.06 23:55:11 (*) (Legacy SDK Generation Skipped)
# 2012.09.06 23:55:11 (*) (All TCL Script Generation Skipped)
# 2012.09.06 23:55:11 (*) (No Libraries Built)
# 2012.09.06 23:55:11 (*) (Contents Generation Skipped)
# 2012.09.06 23:55:11 (*) mk_custom_sdk finishing

# 2012.09.06 23:55:12 (*) Starting generation for system: TETRISCPU.

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# 2012.09.06 23:55:13 (*) Running Generator Program for cpu

# 2012.09.06 23:55:16 (*) Starting Nios II generation
# 2012.09.06 23:55:16 (*)   Checking for plaintext license.
# 2012.09.06 23:55:16 (*)   Plaintext license not found.
# 2012.09.06 23:55:16 (*)   Checking for encrypted license (non-evaluation).
# 2012.09.06 23:55:17 (*)   Encrypted license found.  SOF will not be time-limited.
# 2012.09.06 23:55:17 (*)   Getting CPU configuration settings
# 2012.09.06 23:55:17 (*)   Elaborating CPU configuration settings
# 2012.09.06 23:55:17 (*)   Creating all objects for CPU

# 2012.09.06 23:55:17 (*)     Testbench
# 2012.09.06 23:55:17 (*)     Instruction decoding
# 2012.09.06 23:55:17 (*)       Instruction fields
# 2012.09.06 23:55:17 (*)       Instruction decodes
# 2012.09.06 23:55:19 (*)       Signals for RTL simulation waveforms
# 2012.09.06 23:55:19 (*)       Instruction controls
# 2012.09.06 23:55:19 (*)     Pipeline frontend
# 2012.09.06 23:55:19 (*)     Pipeline backend
# 2012.09.06 23:55:26 (*)   Generating HDL from CPU objects
# 2012.09.06 23:55:30 (*)   Creating encrypted HDL

# 2012.09.06 23:55:32 (*) Done Nios II generation

# 2012.09.06 23:55:33 (*) Running Generator Program for jtag_uart

# 2012.09.06 23:55:35 (*) Running Generator Program for sdram

# 2012.09.06 23:55:37 (*) Running Generator Program for outputsramdata

# 2012.09.06 23:55:39 (*) Running Generator Program for outputxcoord

# 2012.09.06 23:55:41 (*) Running Generator Program for outputycoord

# 2012.09.06 23:55:42 (*) Running Generator Program for keyboardscancode

# 2012.09.06 23:55:44 (*) Running Generator Program for keycounter

# 2012.09.06 23:55:45 (*) Running Generator Program for uart1

# 2012.09.06 23:55:47 (*) Running Generator Program for scoreofplayer

# 2012.09.06 23:55:49 (*) Running Generator Program for pio_flag

# 2012.09.06 23:55:50 (*) Running Generator Program for DM9000A

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# 2012.09.06 23:55:53 (*) Running Test Generator Program for sdram

# 2012.09.06 23:55:54 (*) Making arbitration and system (top) modules.

# 2012.09.06 23:56:03 (*) Generating Quartus symbol for top level: TETRISCPU

# 2012.09.06 23:56:03 (*) Generating Symbol C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU.bsf

# 2012.09.06 23:56:03 (*) Creating command-line system-generation script: C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU_generation_script

# 2012.09.06 23:56:04 (*) Running setup for HDL simulator: modelsim


# 2012.09.06 23:56:04 (*) Completed generation for system: TETRISCPU.
# 2012.09.06 23:56:04 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU.ptf 
  System HDL Model : C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU.v 
  System Generation Script : C:/Users/Gardner/Desktop/tetris_0/lab3/TETRISCPU_generation_script 

# 2012.09.06 23:56:04 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.
