/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * /home/user3/spring12/hw2363/Desktop/new_campus_fighter/test/test_syslib/../../nios_system.ptf
 *
 * Generated: 2012-05-10 12:42:39.749
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios_system"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x01041000
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x01041000
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x01041000
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x00800000
#define NIOS2_BREAK_ADDR 0x01040820

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __BUF
#define __IRTIMER
#define __DE2_PS2

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x01041000
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * sdram_ctrl configuration
 *
 */

#define SDRAM_CTRL_NAME "/dev/sdram_ctrl"
#define SDRAM_CTRL_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_CTRL_BASE 0x00800000
#define SDRAM_CTRL_SPAN 8388608
#define SDRAM_CTRL_REGISTER_DATA_IN 1
#define SDRAM_CTRL_SIM_MODEL_BASE 0
#define SDRAM_CTRL_SDRAM_DATA_WIDTH 16
#define SDRAM_CTRL_SDRAM_ADDR_WIDTH 12
#define SDRAM_CTRL_SDRAM_ROW_WIDTH 12
#define SDRAM_CTRL_SDRAM_COL_WIDTH 8
#define SDRAM_CTRL_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_CTRL_SDRAM_NUM_BANKS 4
#define SDRAM_CTRL_REFRESH_PERIOD 15.625
#define SDRAM_CTRL_POWERUP_DELAY 100.0
#define SDRAM_CTRL_CAS_LATENCY 3
#define SDRAM_CTRL_T_RFC 70.0
#define SDRAM_CTRL_T_RP 20.0
#define SDRAM_CTRL_T_MRD 3
#define SDRAM_CTRL_T_RCD 20.0
#define SDRAM_CTRL_T_AC 5.5
#define SDRAM_CTRL_T_WR 14.0
#define SDRAM_CTRL_INIT_REFRESH_COMMANDS 2
#define SDRAM_CTRL_INIT_NOP_DELAY 0.0
#define SDRAM_CTRL_SHARED_DATA 0
#define SDRAM_CTRL_SDRAM_BANK_WIDTH 2
#define SDRAM_CTRL_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_CTRL_STARVATION_INDICATOR 0
#define SDRAM_CTRL_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_sdram_ctrl altera_avalon_new_sdram_controller

/*
 * sprite_buf configuration
 *
 */

#define SPRITE_BUF_NAME "/dev/sprite_buf"
#define SPRITE_BUF_TYPE "buf"
#define SPRITE_BUF_BASE 0x01000000
#define SPRITE_BUF_SPAN 262144
#define SPRITE_BUF_IRQ 3
#define ALT_MODULE_CLASS_sprite_buf buf

/*
 * irTimer_inst configuration
 *
 */

#define IRTIMER_INST_NAME "/dev/irTimer_inst"
#define IRTIMER_INST_TYPE "irTimer"
#define IRTIMER_INST_BASE 0x01041010
#define IRTIMER_INST_SPAN 4
#define IRTIMER_INST_IRQ 2
#define ALT_MODULE_CLASS_irTimer_inst irTimer

/*
 * de2_ps2_inst configuration
 *
 */

#define DE2_PS2_INST_NAME "/dev/de2_ps2_inst"
#define DE2_PS2_INST_TYPE "de2_ps2"
#define DE2_PS2_INST_BASE 0x01041008
#define DE2_PS2_INST_SPAN 8
#define DE2_PS2_INST_IRQ 1
#define ALT_MODULE_CLASS_de2_ps2_inst de2_ps2

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM_CTRL
#define ALT_RODATA_DEVICE     SDRAM_CTRL
#define ALT_RWDATA_DEVICE     SDRAM_CTRL
#define ALT_EXCEPTIONS_DEVICE SDRAM_CTRL
#define ALT_RESET_DEVICE      SDRAM_CTRL

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */
