# Reading C:/Modeltech/win32/../tcl/vsim/pref.tcl 
# do testbench.fdo 
# Model Technology ModelSim EE vcom 5.2e Compiler 1999.04 Apr 11 1999
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dumb_alu
# -- Compiling architecture behavioral of dumb_alu
# Model Technology ModelSim EE vcom 5.2e Compiler 1999.04 Apr 11 1999
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity testbench
# -- Compiling architecture behavioral of testbench
# -- Loading entity dumb_alu
# vsim -lib work -t 1ps testbench 
# Loading C:/Modeltech/win32/../std.standard
# Loading C:/Modeltech/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech/win32/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavioral)
# Loading work.dumb_alu(behavioral)
# .wave
# .structure
# .signals
destroy .wave
destroy .structure
destroy .signals
quit
