m255
o
dC:\edk_user_repository\lab3\design1
Edesign1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1122885565
Fdesign1.vhdl
l0
L4
V?=?2SP`]8mO:dTG8:A0Mf2
OE;C;5.2e;13
31
o-explicit
Abehavioral
DE work design1 ?=?2SP`]8mO:dTG8:A0Mf2
l13
L12
VE`az>FCO][n4Q9d>5PBM:1
OE;C;5.2e;13
31
M1 ieee std_logic_1164
o-explicit
Etestbench
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1122885654
Ftest_bench.vhd
l0
L6
V;9R2SXo_FEZ_fhLj1kNI]1
OE;C;5.2e;13
31
o-explicit
Abehavioral
DE work design1 ?=?2SP`]8mO:dTG8:A0Mf2
DE work testbench ;9R2SXo_FEZ_fhLj1kNI]1
l22
L10
V:SM26]WNAELCEzN9hRm3j2
OE;C;5.2e;13
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-explicit
