#
# Name of project to compile
#
PROJECT = hello

#
# Verilog source files
#
VERILOG = hello.sv

#
# Quartus executables
#
QUARTUS_SH = quartus_sh --64bit
QUARTUS_PGM = quartus_pgm

#
# Program the FPGA with the bitstream generated by Quartus (the .sof file)
#
# This uses the first (usually only) programming cable in JTAG mode
#
# Run
#
#   quartus_pgm -a
#
# to see a list of all the programming cables and the FPGA devices
# connected to them
#
.PHONY : program
program : $(PROJECT).sof
	$(QUARTUS_PGM) -c 1 -m jtag -o "p;$(PROJECT).sof"

#
# Compile the project from System Verilog source
#
$(PROJECT).sof $(PROJECT).pof : $(PROJECT).qpf $(PROJECT).qsf \
		$(PROJECT).sdc $(VERILOG)
	$(QUARTUS_SH) --flow compile $(PROJECT)


.PHONY : clean
clean :
	rm -rf *.rpt *.summary db incremental_db *.pof *.sof *.done *.smsg *.jdi *.pin

