1 2093 1131 /DDR3/DDR0_A0 TOP
1 2120 1534 /DDR3/DDR0_A0 TOP
1 2247 1138 /DDR3/DDR0_A0 BOTTOM
10 2085 1171 /DDR3/DDR0_A4 TOP
10 2100 1524 /DDR3/DDR0_A4 TOP
10 2183 1093 /DDR3/DDR0_A4 BOTTOM
100 1909 1195 /FPGA_Bank_0_3/DEBUG_IO0 *.Cu
100 2230 1534 /FPGA_Bank_0_3/DEBUG_IO0 TOP
101 1909 1220 /FPGA_Bank_0_3/DEBUG_IO1 *.Cu
101 2230 1544 /FPGA_Bank_0_3/DEBUG_IO1 TOP
102 2080 1404 /FPGA_Bank_0_3/DIFFCLK_A0N TOP
102 2830 1891 /FPGA_Bank_0_3/DIFFCLK_A0N *.Cu
103 2080 1414 /FPGA_Bank_0_3/DIFFCLK_A0P TOP
103 2810 1881 /FPGA_Bank_0_3/DIFFCLK_A0P *.Cu
104 2090 1464 /FPGA_Bank_0_3/DIFFCLK_A1N TOP
104 2830 2071 /FPGA_Bank_0_3/DIFFCLK_A1N *.Cu
105 2080 1454 /FPGA_Bank_0_3/DIFFCLK_A1P TOP
105 2810 2061 /FPGA_Bank_0_3/DIFFCLK_A1P *.Cu
106 2070 1394 /FPGA_Bank_0_3/DIFFCLK_B0N TOP
106 2765 1871 /FPGA_Bank_0_3/DIFFCLK_B0N *.Cu
107 2080 1394 /FPGA_Bank_0_3/DIFFCLK_B0P TOP
107 2785 1861 /FPGA_Bank_0_3/DIFFCLK_B0P *.Cu
108 2090 1444 /FPGA_Bank_0_3/DIFFCLK_B1N TOP
108 2765 2051 /FPGA_Bank_0_3/DIFFCLK_B1N *.Cu
109 2100 1434 /FPGA_Bank_0_3/DIFFCLK_B1P TOP
109 2785 2041 /FPGA_Bank_0_3/DIFFCLK_B1P *.Cu
11 2085 1123 /DDR3/DDR0_A5 TOP
11 2140 1524 /DDR3/DDR0_A5 TOP
11 2246 1164 /DDR3/DDR0_A5 BOTTOM
110 2060 1364 /FPGA_Bank_0_3/DIFFCLK_XN TOP
110 2830 1731 /FPGA_Bank_0_3/DIFFCLK_XN *.Cu
111 2060 1374 /FPGA_Bank_0_3/DIFFCLK_XP TOP
111 2810 1721 /FPGA_Bank_0_3/DIFFCLK_XP *.Cu
112 2050 1374 /FPGA_Bank_0_3/DIFFIO_A0N TOP
112 2830 1631 /FPGA_Bank_0_3/DIFFIO_A0N *.Cu
113 2060 1384 /FPGA_Bank_0_3/DIFFIO_A0P TOP
113 2810 1621 /FPGA_Bank_0_3/DIFFIO_A0P *.Cu
114 2030 1374 /FPGA_Bank_0_3/DIFFIO_A1N TOP
114 2810 1761 /FPGA_Bank_0_3/DIFFIO_A1N *.Cu
115 2040 1374 /FPGA_Bank_0_3/DIFFIO_A1P TOP
115 2830 1751 /FPGA_Bank_0_3/DIFFIO_A1P *.Cu
116 2090 1404 /FPGA_Bank_0_3/DIFFIO_A2N TOP
116 2830 1811 /FPGA_Bank_0_3/DIFFIO_A2N *.Cu
117 2100 1414 /FPGA_Bank_0_3/DIFFIO_A2P TOP
117 2810 1801 /FPGA_Bank_0_3/DIFFIO_A2P *.Cu
118 2090 1424 /FPGA_Bank_0_3/DIFFIO_A3N TOP
118 2830 1851 /FPGA_Bank_0_3/DIFFIO_A3N *.Cu
119 2100 1424 /FPGA_Bank_0_3/DIFFIO_A3P TOP
119 2810 1841 /FPGA_Bank_0_3/DIFFIO_A3P *.Cu
12 2077 1171 /DDR3/DDR0_A6 TOP
12 2130 1514 /DDR3/DDR0_A6 TOP
12 2212 1093 /DDR3/DDR0_A6 BOTTOM
120 2070 1494 /FPGA_Bank_0_3/DIFFIO_A4N TOP
120 2830 1951 /FPGA_Bank_0_3/DIFFIO_A4N *.Cu
121 2070 1504 /FPGA_Bank_0_3/DIFFIO_A4P TOP
121 2810 1941 /FPGA_Bank_0_3/DIFFIO_A4P *.Cu
122 2030 1514 /FPGA_Bank_0_3/DIFFIO_A5N TOP
122 2830 1991 /FPGA_Bank_0_3/DIFFIO_A5N *.Cu
123 2050 1514 /FPGA_Bank_0_3/DIFFIO_A5P TOP
123 2810 1981 /FPGA_Bank_0_3/DIFFIO_A5P *.Cu
124 2030 1534 /FPGA_Bank_0_3/DIFFIO_A6N TOP
124 2830 2031 /FPGA_Bank_0_3/DIFFIO_A6N *.Cu
125 2040 1534 /FPGA_Bank_0_3/DIFFIO_A6P TOP
125 2810 2021 /FPGA_Bank_0_3/DIFFIO_A6P *.Cu
126 2030 1354 /FPGA_Bank_0_3/DIFFIO_B0N TOP
126 2830 1651 /FPGA_Bank_0_3/DIFFIO_B0N *.Cu
127 2040 1354 /FPGA_Bank_0_3/DIFFIO_B0P TOP
127 2810 1641 /FPGA_Bank_0_3/DIFFIO_B0P *.Cu
128 2080 1384 /FPGA_Bank_0_3/DIFFIO_B1N TOP
128 2785 1741 /FPGA_Bank_0_3/DIFFIO_B1N *.Cu
129 2090 1394 /FPGA_Bank_0_3/DIFFIO_B1P TOP
129 2765 1731 /FPGA_Bank_0_3/DIFFIO_B1P *.Cu
13 2077 1123 /DDR3/DDR0_A7 TOP
13 2120 1494 /DDR3/DDR0_A7 TOP
13 2246 1172 /DDR3/DDR0_A7 BOTTOM
130 2030 1384 /FPGA_Bank_0_3/DIFFIO_B2N TOP
130 2765 1791 /FPGA_Bank_0_3/DIFFIO_B2N *.Cu
131 2050 1384 /FPGA_Bank_0_3/DIFFIO_B2P TOP
131 2785 1781 /FPGA_Bank_0_3/DIFFIO_B2P *.Cu
132 2100 1444 /FPGA_Bank_0_3/DIFFIO_B3N TOP
132 2765 1831 /FPGA_Bank_0_3/DIFFIO_B3N *.Cu
133 2100 1454 /FPGA_Bank_0_3/DIFFIO_B3P TOP
133 2785 1821 /FPGA_Bank_0_3/DIFFIO_B3P *.Cu
134 2060 1504 /FPGA_Bank_0_3/DIFFIO_B4N TOP
134 2765 1931 /FPGA_Bank_0_3/DIFFIO_B4N *.Cu
135 2060 1514 /FPGA_Bank_0_3/DIFFIO_B4P TOP
135 2785 1921 /FPGA_Bank_0_3/DIFFIO_B4P *.Cu
136 2030 1504 /FPGA_Bank_0_3/DIFFIO_B5N TOP
136 2765 1971 /FPGA_Bank_0_3/DIFFIO_B5N *.Cu
137 2050 1504 /FPGA_Bank_0_3/DIFFIO_B5P TOP
137 2785 1961 /FPGA_Bank_0_3/DIFFIO_B5P *.Cu
138 2030 1524 /FPGA_Bank_0_3/DIFFIO_B6N TOP
138 2765 2011 /FPGA_Bank_0_3/DIFFIO_B6N *.Cu
139 2040 1524 /FPGA_Bank_0_3/DIFFIO_B6P TOP
139 2785 2001 /FPGA_Bank_0_3/DIFFIO_B6P *.Cu
14 2069 1171 /DDR3/DDR0_A8 TOP
14 2090 1524 /DDR3/DDR0_A8 TOP
14 2220 1093 /DDR3/DDR0_A8 BOTTOM
140 2030 1364 /FPGA_Bank_0_3/DIFFIO_XN TOP
140 2785 1681 /FPGA_Bank_0_3/DIFFIO_XN *.Cu
141 2050 1364 /FPGA_Bank_0_3/DIFFIO_XP TOP
141 2785 1661 /FPGA_Bank_0_3/DIFFIO_XP *.Cu
142 2080 1474 /FPGA_Bank_0_3/DIFFIO_YN TOP
142 2765 1711 /FPGA_Bank_0_3/DIFFIO_YN *.Cu
143 2080 1484 /FPGA_Bank_0_3/DIFFIO_YP TOP
143 2810 1781 /FPGA_Bank_0_3/DIFFIO_YP *.Cu
144 2080 1464 /FPGA_Bank_0_3/DIFFIO_ZN TOP
144 2765 1891 /FPGA_Bank_0_3/DIFFIO_ZN *.Cu
145 2090 1474 /FPGA_Bank_0_3/DIFFIO_ZP TOP
145 2830 1911 /FPGA_Bank_0_3/DIFFIO_ZP *.Cu
146 2050 1524 /FPGA_Bank_0_3/HSWAP TOP
146 2249 1314 /FPGA_Bank_0_3/HSWAP BOTTOM
147 2080 1434 /FPGA_Bank_0_3/MGT135MHz_N TOP
147 2290 1462 /FPGA_Bank_0_3/MGT135MHz_N TOP
148 2070 1434 /FPGA_Bank_0_3/MGT135MHz_P TOP
148 2289 1478 /FPGA_Bank_0_3/MGT135MHz_P TOP
149 2120 1334 /FPGA_Bank_0_3/MGTREFCLK0_101_N TOP
149 2282 1429 /FPGA_Bank_0_3/MGTREFCLK0_101_N TOP
15 2077 1131 /DDR3/DDR0_A9 TOP
15 2090 1544 /DDR3/DDR0_A9 TOP
15 2247 1130 /DDR3/DDR0_A9 BOTTOM
150 2120 1344 /FPGA_Bank_0_3/MGTREFCLK0_101_P TOP
150 2271 1429 /FPGA_Bank_0_3/MGTREFCLK0_101_P TOP
151 2060 1444 /FPGA_Bank_0_3/MGTSMACLK_N TOP
151 2318 1420 /FPGA_Bank_0_3/MGTSMACLK_N TOP
152 2050 1444 /FPGA_Bank_0_3/MGTSMACLK_P TOP
152 2306 1420 /FPGA_Bank_0_3/MGTSMACLK_P TOP
153 2060 1524 /FPGA_Bank_0_3/PCIE_RESET TOP
153 2810 1681 /FPGA_Bank_0_3/PCIE_RESET *.Cu
154 2090 1484 /FPGA_Bank_0_3/PCIO0 TOP
154 2573 1331 /FPGA_Bank_0_3/PCIO0 TOP
155 2110 1484 /FPGA_Bank_0_3/PCIO1 TOP
155 2610 1282 /FPGA_Bank_0_3/PCIO1 *.Cu
156 2100 1474 /FPGA_Bank_0_3/PCIO2 TOP
156 2610 1257 /FPGA_Bank_0_3/PCIO2 *.Cu
157 2080 1504 /FPGA_Bank_0_3/PCIO3 TOP
157 2636 1257 /FPGA_Bank_0_3/PCIO3 *.Cu
157 2637 1226 /FPGA_Bank_0_3/PCIO3 BOTTOM
158 2150 1494 /FPGA_Bank_0_3/SMCLK TOP
158 2785 1621 /FPGA_Bank_0_3/SMCLK *.Cu
159 2150 1484 /FPGA_Bank_0_3/SMDATA TOP
159 2765 1631 /FPGA_Bank_0_3/SMDATA *.Cu
16 2101 1123 /DDR3/DDR0_BA0 TOP
16 2110 1524 /DDR3/DDR0_BA0 TOP
16 2246 1156 /DDR3/DDR0_BA0 BOTTOM
160 1899 1369 /FPGA_Bank_0_3/SWITCH TOP
160 2220 1524 /FPGA_Bank_0_3/SWITCH TOP
161 2160 1354 /FPGA_Bank_1_2/CY-IFCLK TOP
161 2298 1805 /FPGA_Bank_1_2/CY-IFCLK TOP
162 2090 1334 /FPGA_Bank_1_2/CYPRESS-RESET TOP
162 2105 2012 /FPGA_Bank_1_2/CYPRESS-RESET *.Cu
163 2135 1799 /FPGA_Bank_1_2/CY_CTL0 TOP
163 2150 1394 /FPGA_Bank_1_2/CY_CTL0 TOP
164 2135 1805 /FPGA_Bank_1_2/CY_CTL1 TOP
164 2160 1394 /FPGA_Bank_1_2/CY_CTL1 TOP
165 2135 1812 /FPGA_Bank_1_2/CY_CTL2 TOP
165 2170 1404 /FPGA_Bank_1_2/CY_CTL2 TOP
166 2135 1779 /FPGA_Bank_1_2/CY_CTL3 TOP
166 2140 1374 /FPGA_Bank_1_2/CY_CTL3 TOP
167 2135 1786 /FPGA_Bank_1_2/CY_CTL4 TOP
167 2140 1384 /FPGA_Bank_1_2/CY_CTL4 TOP
168 2135 1942 /FPGA_Bank_1_2/CY_CTL5 TOP
168 2170 1394 /FPGA_Bank_1_2/CY_CTL5 TOP
169 2050 1354 /FPGA_Bank_1_2/CY_FD0 TOP
169 2259 1762 /FPGA_Bank_1_2/CY_FD0 TOP
17 2093 1171 /DDR3/DDR0_BA1 TOP
17 2110 1544 /DDR3/DDR0_BA1 TOP
17 2149 1092 /DDR3/DDR0_BA1 BOTTOM
170 2050 1334 /FPGA_Bank_1_2/CY_FD1 TOP
170 2252 1762 /FPGA_Bank_1_2/CY_FD1 TOP
171 2080 1344 /FPGA_Bank_1_2/CY_FD10 TOP
171 2161 1985 /FPGA_Bank_1_2/CY_FD10 TOP
172 2080 1334 /FPGA_Bank_1_2/CY_FD11 TOP
172 2168 1985 /FPGA_Bank_1_2/CY_FD11 TOP
173 2070 1354 /FPGA_Bank_1_2/CY_FD12 TOP
173 2246 1985 /FPGA_Bank_1_2/CY_FD12 TOP
174 2070 1334 /FPGA_Bank_1_2/CY_FD13 TOP
174 2252 1985 /FPGA_Bank_1_2/CY_FD13 TOP
175 2110 1364 /FPGA_Bank_1_2/CY_FD14 TOP
175 2259 1985 /FPGA_Bank_1_2/CY_FD14 TOP
176 2100 1354 /FPGA_Bank_1_2/CY_FD15 TOP
176 2265 1985 /FPGA_Bank_1_2/CY_FD15 TOP
177 2130 1404 /FPGA_Bank_1_2/CY_FD2 TOP
177 2246 1762 /FPGA_Bank_1_2/CY_FD2 TOP
178 2120 1394 /FPGA_Bank_1_2/CY_FD3 TOP
178 2239 1762 /FPGA_Bank_1_2/CY_FD3 TOP
179 2060 1344 /FPGA_Bank_1_2/CY_FD4 TOP
179 2194 1762 /FPGA_Bank_1_2/CY_FD4 TOP
18 2100 1544 /DDR3/DDR0_BA2 TOP
18 2101 1131 /DDR3/DDR0_BA2 TOP
18 2247 1114 /DDR3/DDR0_BA2 BOTTOM
180 2060 1334 /FPGA_Bank_1_2/CY_FD5 TOP
180 2187 1762 /FPGA_Bank_1_2/CY_FD5 TOP
181 2090 1364 /FPGA_Bank_1_2/CY_FD6 TOP
181 2181 1762 /FPGA_Bank_1_2/CY_FD6 TOP
182 2080 1354 /FPGA_Bank_1_2/CY_FD7 TOP
182 2174 1762 /FPGA_Bank_1_2/CY_FD7 TOP
183 2100 1374 /FPGA_Bank_1_2/CY_FD8 TOP
183 2135 1968 /FPGA_Bank_1_2/CY_FD8 TOP
184 2100 1364 /FPGA_Bank_1_2/CY_FD9 TOP
184 2155 1985 /FPGA_Bank_1_2/CY_FD9 TOP
185 2174 1985 /FPGA_Bank_1_2/CY_INT5 TOP
185 2180 1364 /FPGA_Bank_1_2/CY_INT5 TOP
186 2080 1374 /FPGA_Bank_1_2/CY_PA0 TOP
186 2135 1883 /FPGA_Bank_1_2/CY_PA0 TOP
187 2080 1364 /FPGA_Bank_1_2/CY_PA1 TOP
187 2135 1890 /FPGA_Bank_1_2/CY_PA1 TOP
188 2100 1394 /FPGA_Bank_1_2/CY_PA2 TOP
188 2135 1896 /FPGA_Bank_1_2/CY_PA2 TOP
189 2100 1384 /FPGA_Bank_1_2/CY_PA3 TOP
189 2135 1903 /FPGA_Bank_1_2/CY_PA3 TOP
19 2117 1131 /DDR3/DDR0_CAS_N TOP
19 2140 1514 /DDR3/DDR0_CAS_N TOP
19 2167 1093 /DDR3/DDR0_CAS_N BOTTOM
190 2040 1344 /FPGA_Bank_1_2/CY_PA4 TOP
190 2135 1909 /FPGA_Bank_1_2/CY_PA4 TOP
191 2040 1334 /FPGA_Bank_1_2/CY_PA5 TOP
191 2135 1916 /FPGA_Bank_1_2/CY_PA5 TOP
192 2110 1394 /FPGA_Bank_1_2/CY_PA6 TOP
192 2135 1922 /FPGA_Bank_1_2/CY_PA6 TOP
193 2110 1384 /FPGA_Bank_1_2/CY_PA7 TOP
193 2135 1929 /FPGA_Bank_1_2/CY_PA7 TOP
194 2135 1818 /FPGA_Bank_1_2/CY_PC0 TOP
194 2190 1354 /FPGA_Bank_1_2/CY_PC0 TOP
195 2135 1825 /FPGA_Bank_1_2/CY_PC1 TOP
195 2190 1334 /FPGA_Bank_1_2/CY_PC1 TOP
196 2135 1831 /FPGA_Bank_1_2/CY_PC2 TOP
196 2200 1344 /FPGA_Bank_1_2/CY_PC2 TOP
197 2135 1838 /FPGA_Bank_1_2/CY_PC3 TOP
197 2200 1334 /FPGA_Bank_1_2/CY_PC3 TOP
198 2135 1844 /FPGA_Bank_1_2/CY_PC4 TOP
198 2210 1354 /FPGA_Bank_1_2/CY_PC4 TOP
199 2135 1851 /FPGA_Bank_1_2/CY_PC5 TOP
199 2210 1334 /FPGA_Bank_1_2/CY_PC5 TOP
2 2085 1163 /DDR3/DDR0_A1 TOP
2 2120 1544 /DDR3/DDR0_A1 TOP
2 2236 1093 /DDR3/DDR0_A1 BOTTOM
20 2080 1534 /DDR3/DDR0_CKE TOP
20 2117 1179 /DDR3/DDR0_CKE TOP
20 2142 1109 /DDR3/DDR0_CKE BOTTOM
200 2135 1857 /FPGA_Bank_1_2/CY_PC6 TOP
200 2220 1344 /FPGA_Bank_1_2/CY_PC6 TOP
201 2135 1864 /FPGA_Bank_1_2/CY_PC7 TOP
201 2220 1334 /FPGA_Bank_1_2/CY_PC7 TOP
202 2120 1364 /FPGA_Bank_1_2/CY_RD TOP
202 2278 1762 /FPGA_Bank_1_2/CY_RD TOP
203 2160 1364 /FPGA_Bank_1_2/CY_RD0 TOP
203 2298 1955 /FPGA_Bank_1_2/CY_RD0 TOP
204 2170 1364 /FPGA_Bank_1_2/CY_RD1 TOP
204 2298 1948 /FPGA_Bank_1_2/CY_RD1 TOP
205 2140 1394 /FPGA_Bank_1_2/CY_RD2 TOP
205 2298 1942 /FPGA_Bank_1_2/CY_RD2 TOP
206 2150 1404 /FPGA_Bank_1_2/CY_RD3 TOP
206 2298 1935 /FPGA_Bank_1_2/CY_RD3 TOP
207 2190 1364 /FPGA_Bank_1_2/CY_RD4 TOP
207 2298 1929 /FPGA_Bank_1_2/CY_RD4 TOP
208 2180 1354 /FPGA_Bank_1_2/CY_RD5 TOP
208 2298 1922 /FPGA_Bank_1_2/CY_RD5 TOP
209 2160 1374 /FPGA_Bank_1_2/CY_RXD0 TOP
209 2213 1762 /FPGA_Bank_1_2/CY_RXD0 TOP
21 2117 1163 /DDR3/DDR0_CK_N TOP
21 2120 1524 /DDR3/DDR0_CK_N TOP
21 2153 1144 /DDR3/DDR0_CK_N BOTTOM
210 2160 1384 /FPGA_Bank_1_2/CY_RXD1 TOP
210 2200 1762 /FPGA_Bank_1_2/CY_RXD1 TOP
211 2090 1354 /FPGA_Bank_1_2/CY_T0 TOP
211 2298 1825 /FPGA_Bank_1_2/CY_T0 TOP
212 2180 1384 /FPGA_Bank_1_2/CY_TXD0 TOP
212 2220 1762 /FPGA_Bank_1_2/CY_TXD0 TOP
213 2170 1384 /FPGA_Bank_1_2/CY_TXD1 TOP
213 2207 1762 /FPGA_Bank_1_2/CY_TXD1 TOP
214 2120 1374 /FPGA_Bank_1_2/CY_WR TOP
214 2272 1762 /FPGA_Bank_1_2/CY_WR TOP
215 2210 1444 /FPGA_Bank_1_2/DPRXHPD TOP
215 2563 2142 /FPGA_Bank_1_2/DPRXHPD BOTTOM
215 2568 2131 /FPGA_Bank_1_2/DPRXHPD TOP
216 2200 1444 /FPGA_Bank_1_2/DPTXHPD TOP
216 2330 2137 /FPGA_Bank_1_2/DPTXHPD BOTTOM
216 2339 2131 /FPGA_Bank_1_2/DPTXHPD TOP
217 2060 1600 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO TOP
217 2071 1637 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO TOP
217 2230 1344 /FPGA_Bank_1_2/FPGA_M0_CMP_MISO TOP
218 2025 1637 /FPGA_Bank_1_2/FPGA_M1 TOP
218 2037 1600 /FPGA_Bank_1_2/FPGA_M1 TOP
218 2220 1364 /FPGA_Bank_1_2/FPGA_M1 TOP
219 2007 1349 /FPGA_Bank_1_2/INIT_B BOTTOM
219 2220 1514 /FPGA_Bank_1_2/INIT_B TOP
219 2269 2019 /FPGA_Bank_1_2/INIT_B TOP
22 2120 1514 /DDR3/DDR0_CK_P TOP
22 2125 1163 /DDR3/DDR0_CK_P TOP
22 2144 1144 /DDR3/DDR0_CK_P BOTTOM
220 1245 1236 /FPGA_Bank_1_2/SD_CLK 
220 1260 1265 /FPGA_Bank_1_2/SD_CLK *.Cu
220 2180 1484 /FPGA_Bank_1_2/SD_CLK TOP
221 1245 1258 /FPGA_Bank_1_2/SD_CMD 
221 1285 1265 /FPGA_Bank_1_2/SD_CMD *.Cu
221 1287 1165 /FPGA_Bank_1_2/SD_CMD TOP
221 2190 1494 /FPGA_Bank_1_2/SD_CMD TOP
222 1235 1265 /FPGA_Bank_1_2/SD_DAT0 *.Cu
222 1245 1214 /FPGA_Bank_1_2/SD_DAT0 
222 1287 1182 /FPGA_Bank_1_2/SD_DAT0 TOP
222 2230 1514 /FPGA_Bank_1_2/SD_DAT0 TOP
223 1209 1265 /FPGA_Bank_1_2/SD_DAT1 *.Cu
223 1245 1203 /FPGA_Bank_1_2/SD_DAT1 
223 1287 1200 /FPGA_Bank_1_2/SD_DAT1 TOP
223 2240 1514 /FPGA_Bank_1_2/SD_DAT1 TOP
224 1245 1280 /FPGA_Bank_1_2/SD_DAT2 
224 1287 1129 /FPGA_Bank_1_2/SD_DAT2 TOP
224 1336 1265 /FPGA_Bank_1_2/SD_DAT2 *.Cu
224 2240 1504 /FPGA_Bank_1_2/SD_DAT2 TOP
225 1241 1269 /FPGA_Bank_1_2/SD_DAT3 
225 1287 1147 /FPGA_Bank_1_2/SD_DAT3 TOP
225 1311 1265 /FPGA_Bank_1_2/SD_DAT3 *.Cu
225 2220 1504 /FPGA_Bank_1_2/SD_DAT3 TOP
226 1845 1532 /FPGA_Bank_1_2/SPI_CLK TOP
226 2220 1354 /FPGA_Bank_1_2/SPI_CLK TOP
227 1845 1534 /FPGA_Bank_1_2/SPI_CS_N BOTTOM
227 1910 1557 /FPGA_Bank_1_2/SPI_CS_N TOP
227 2230 1524 /FPGA_Bank_1_2/SPI_CS_N TOP
228 1978 1551 /FPGA_Bank_1_2/SPI_D1_MISO2 TOP
228 2170 1424 /FPGA_Bank_1_2/SPI_D1_MISO2 TOP
229 1845 1545 /FPGA_Bank_1_2/SPI_D2_MISO3 TOP
229 1930 1519 /FPGA_Bank_1_2/SPI_D2_MISO3 BOTTOM
229 2180 1414 /FPGA_Bank_1_2/SPI_D2_MISO3 TOP
23 2157 1131 /DDR3/DDR0_DQ0 TOP
23 2170 1524 /DDR3/DDR0_DQ0 TOP
230 1979 1526 /FPGA_Bank_1_2/SPI_DO_DIN_MISO1 TOP
230 2230 1354 /FPGA_Bank_1_2/SPI_DO_DIN_MISO1 TOP
231 2240 1354 /FPGA_Bank_1_2/SPI_MOSI_CSI_N_MISO0 TOP
232 1994 2001 /FPGA_Bank_1_2/TMDS_RX1_0_N BOTTOM
232 1995 2032 /FPGA_Bank_1_2/TMDS_RX1_0_N TOP
232 1995 2089 /FPGA_Bank_1_2/TMDS_RX1_0_N TOP
232 1995 2176 /FPGA_Bank_1_2/TMDS_RX1_0_N TOP
232 2110 1334 /FPGA_Bank_1_2/TMDS_RX1_0_N TOP
233 2005 2001 /FPGA_Bank_1_2/TMDS_RX1_0_P BOTTOM
233 2005 2032 /FPGA_Bank_1_2/TMDS_RX1_0_P TOP
233 2005 2089 /FPGA_Bank_1_2/TMDS_RX1_0_P TOP
233 2005 2176 /FPGA_Bank_1_2/TMDS_RX1_0_P TOP
233 2110 1354 /FPGA_Bank_1_2/TMDS_RX1_0_P TOP
234 2010 2032 /FPGA_Bank_1_2/TMDS_RX1_1_N TOP
234 2010 2036 /FPGA_Bank_1_2/TMDS_RX1_1_N BOTTOM
234 2010 2089 /FPGA_Bank_1_2/TMDS_RX1_1_N TOP
234 2010 2176 /FPGA_Bank_1_2/TMDS_RX1_1_N TOP
234 2100 1334 /FPGA_Bank_1_2/TMDS_RX1_1_N TOP
235 2020 2032 /FPGA_Bank_1_2/TMDS_RX1_1_P TOP
235 2020 2036 /FPGA_Bank_1_2/TMDS_RX1_1_P BOTTOM
235 2020 2089 /FPGA_Bank_1_2/TMDS_RX1_1_P TOP
235 2020 2176 /FPGA_Bank_1_2/TMDS_RX1_1_P TOP
235 2100 1344 /FPGA_Bank_1_2/TMDS_RX1_1_P TOP
236 2024 2001 /FPGA_Bank_1_2/TMDS_RX1_2_N BOTTOM
236 2025 2032 /FPGA_Bank_1_2/TMDS_RX1_2_N TOP
236 2025 2089 /FPGA_Bank_1_2/TMDS_RX1_2_N TOP
236 2025 2176 /FPGA_Bank_1_2/TMDS_RX1_2_N TOP
236 2130 1364 /FPGA_Bank_1_2/TMDS_RX1_2_N TOP
237 2035 2001 /FPGA_Bank_1_2/TMDS_RX1_2_P BOTTOM
237 2035 2032 /FPGA_Bank_1_2/TMDS_RX1_2_P TOP
237 2035 2089 /FPGA_Bank_1_2/TMDS_RX1_2_P TOP
237 2035 2176 /FPGA_Bank_1_2/TMDS_RX1_2_P TOP
237 2120 1354 /FPGA_Bank_1_2/TMDS_RX1_2_P TOP
238 1889 1956 /FPGA_Bank_1_2/TMDS_RX1_CEC *.Cu
238 1922 2061 /FPGA_Bank_1_2/TMDS_RX1_CEC TOP
238 1975 2032 /FPGA_Bank_1_2/TMDS_RX1_CEC TOP
238 2120 1384 /FPGA_Bank_1_2/TMDS_RX1_CEC TOP
239 1979 2036 /FPGA_Bank_1_2/TMDS_RX1_CLK_N BOTTOM
239 1980 2032 /FPGA_Bank_1_2/TMDS_RX1_CLK_N TOP
239 1980 2089 /FPGA_Bank_1_2/TMDS_RX1_CLK_N TOP
239 1980 2176 /FPGA_Bank_1_2/TMDS_RX1_CLK_N TOP
239 2140 1364 /FPGA_Bank_1_2/TMDS_RX1_CLK_N TOP
24 2149 1163 /DDR3/DDR0_DQ1 TOP
24 2170 1544 /DDR3/DDR0_DQ1 TOP
240 1990 2032 /FPGA_Bank_1_2/TMDS_RX1_CLK_P TOP
240 1990 2036 /FPGA_Bank_1_2/TMDS_RX1_CLK_P BOTTOM
240 1990 2089 /FPGA_Bank_1_2/TMDS_RX1_CLK_P TOP
240 1990 2176 /FPGA_Bank_1_2/TMDS_RX1_CLK_P TOP
240 2140 1354 /FPGA_Bank_1_2/TMDS_RX1_CLK_P TOP
241 1868 1942 /FPGA_Bank_1_2/TMDS_RX1_HOT *.Cu
241 1960 2032 /FPGA_Bank_1_2/TMDS_RX1_HOT TOP
241 2200 1364 /FPGA_Bank_1_2/TMDS_RX1_HOT TOP
242 1850 2066 /FPGA_Bank_1_2/TMDS_RX1_SCL *.Cu
242 1922 2038 /FPGA_Bank_1_2/TMDS_RX1_SCL TOP
242 1970 2032 /FPGA_Bank_1_2/TMDS_RX1_SCL TOP
242 2130 1384 /FPGA_Bank_1_2/TMDS_RX1_SCL TOP
243 1850 2040 /FPGA_Bank_1_2/TMDS_RX1_SDA *.Cu
243 1922 2015 /FPGA_Bank_1_2/TMDS_RX1_SDA TOP
243 1965 2032 /FPGA_Bank_1_2/TMDS_RX1_SDA TOP
243 2180 1374 /FPGA_Bank_1_2/TMDS_RX1_SDA TOP
244 1761 2002 /FPGA_Bank_1_2/TMDS_RX2_0_N BOTTOM
244 1761 2032 /FPGA_Bank_1_2/TMDS_RX2_0_N TOP
244 1761 2089 /FPGA_Bank_1_2/TMDS_RX2_0_N TOP
244 1761 2176 /FPGA_Bank_1_2/TMDS_RX2_0_N TOP
244 2140 1334 /FPGA_Bank_1_2/TMDS_RX2_0_N TOP
245 1771 2002 /FPGA_Bank_1_2/TMDS_RX2_0_P BOTTOM
245 1771 2032 /FPGA_Bank_1_2/TMDS_RX2_0_P TOP
245 1771 2089 /FPGA_Bank_1_2/TMDS_RX2_0_P TOP
245 1771 2176 /FPGA_Bank_1_2/TMDS_RX2_0_P TOP
245 2140 1344 /FPGA_Bank_1_2/TMDS_RX2_0_P TOP
246 1776 2032 /FPGA_Bank_1_2/TMDS_RX2_1_N TOP
246 1776 2036 /FPGA_Bank_1_2/TMDS_RX2_1_N BOTTOM
246 1776 2089 /FPGA_Bank_1_2/TMDS_RX2_1_N TOP
246 1776 2176 /FPGA_Bank_1_2/TMDS_RX2_1_N TOP
246 2150 1334 /FPGA_Bank_1_2/TMDS_RX2_1_N TOP
247 1786 2032 /FPGA_Bank_1_2/TMDS_RX2_1_P TOP
247 1786 2036 /FPGA_Bank_1_2/TMDS_RX2_1_P BOTTOM
247 1786 2089 /FPGA_Bank_1_2/TMDS_RX2_1_P TOP
247 1786 2176 /FPGA_Bank_1_2/TMDS_RX2_1_P TOP
247 2150 1354 /FPGA_Bank_1_2/TMDS_RX2_1_P TOP
248 1791 2001 /FPGA_Bank_1_2/TMDS_RX2_2_N BOTTOM
248 1791 2032 /FPGA_Bank_1_2/TMDS_RX2_2_N TOP
248 1791 2089 /FPGA_Bank_1_2/TMDS_RX2_2_N TOP
248 1791 2176 /FPGA_Bank_1_2/TMDS_RX2_2_N TOP
248 2160 1334 /FPGA_Bank_1_2/TMDS_RX2_2_N TOP
249 1801 2001 /FPGA_Bank_1_2/TMDS_RX2_2_P BOTTOM
249 1801 2032 /FPGA_Bank_1_2/TMDS_RX2_2_P TOP
249 1801 2089 /FPGA_Bank_1_2/TMDS_RX2_2_P TOP
249 1801 2176 /FPGA_Bank_1_2/TMDS_RX2_2_P TOP
249 2160 1344 /FPGA_Bank_1_2/TMDS_RX2_2_P TOP
25 2173 1171 /DDR3/DDR0_DQ10 TOP
25 2190 1524 /DDR3/DDR0_DQ10 TOP
250 1693 2061 /FPGA_Bank_1_2/TMDS_RX2_CEC TOP
250 1741 1977 /FPGA_Bank_1_2/TMDS_RX2_CEC *.Cu
250 1741 2032 /FPGA_Bank_1_2/TMDS_RX2_CEC TOP
250 2180 1334 /FPGA_Bank_1_2/TMDS_RX2_CEC TOP
251 1746 2032 /FPGA_Bank_1_2/TMDS_RX2_CLK_N TOP
251 1746 2036 /FPGA_Bank_1_2/TMDS_RX2_CLK_N BOTTOM
251 1746 2089 /FPGA_Bank_1_2/TMDS_RX2_CLK_N TOP
251 1746 2176 /FPGA_Bank_1_2/TMDS_RX2_CLK_N TOP
251 2130 1334 /FPGA_Bank_1_2/TMDS_RX2_CLK_N TOP
252 1756 2032 /FPGA_Bank_1_2/TMDS_RX2_CLK_P TOP
252 1756 2036 /FPGA_Bank_1_2/TMDS_RX2_CLK_P BOTTOM
252 1756 2089 /FPGA_Bank_1_2/TMDS_RX2_CLK_P TOP
252 1756 2176 /FPGA_Bank_1_2/TMDS_RX2_CLK_P TOP
252 2130 1354 /FPGA_Bank_1_2/TMDS_RX2_CLK_P TOP
253 1719 2000 /FPGA_Bank_1_2/TMDS_RX2_HOT *.Cu
253 1726 2032 /FPGA_Bank_1_2/TMDS_RX2_HOT TOP
253 2170 1354 /FPGA_Bank_1_2/TMDS_RX2_HOT TOP
254 1624 2055 /FPGA_Bank_1_2/TMDS_RX2_SCL *.Cu
254 1693 2038 /FPGA_Bank_1_2/TMDS_RX2_SCL TOP
254 1736 2032 /FPGA_Bank_1_2/TMDS_RX2_SCL TOP
254 2180 1344 /FPGA_Bank_1_2/TMDS_RX2_SCL TOP
255 1624 2029 /FPGA_Bank_1_2/TMDS_RX2_SDA *.Cu
255 1693 2015 /FPGA_Bank_1_2/TMDS_RX2_SDA TOP
255 1731 2032 /FPGA_Bank_1_2/TMDS_RX2_SDA TOP
255 2170 1334 /FPGA_Bank_1_2/TMDS_RX2_SDA TOP
256 1293 2032 /FPGA_Bank_1_2/TMDS_TX1_0_N TOP
256 1293 2089 /FPGA_Bank_1_2/TMDS_TX1_0_N TOP
256 1294 2176 /FPGA_Bank_1_2/TMDS_TX1_0_N TOP
256 2220 1434 /FPGA_Bank_1_2/TMDS_TX1_0_N TOP
257 1303 2032 /FPGA_Bank_1_2/TMDS_TX1_0_P TOP
257 1303 2089 /FPGA_Bank_1_2/TMDS_TX1_0_P TOP
257 1304 2176 /FPGA_Bank_1_2/TMDS_TX1_0_P TOP
257 2210 1434 /FPGA_Bank_1_2/TMDS_TX1_0_P TOP
258 1308 2032 /FPGA_Bank_1_2/TMDS_TX1_1_N TOP
258 1308 2089 /FPGA_Bank_1_2/TMDS_TX1_1_N TOP
258 1309 2176 /FPGA_Bank_1_2/TMDS_TX1_1_N TOP
258 2240 1454 /FPGA_Bank_1_2/TMDS_TX1_1_N TOP
259 1318 2032 /FPGA_Bank_1_2/TMDS_TX1_1_P TOP
259 1318 2089 /FPGA_Bank_1_2/TMDS_TX1_1_P TOP
259 1319 2176 /FPGA_Bank_1_2/TMDS_TX1_1_P TOP
259 2230 1454 /FPGA_Bank_1_2/TMDS_TX1_1_P TOP
26 2173 1123 /DDR3/DDR0_DQ11 TOP
26 2190 1544 /DDR3/DDR0_DQ11 TOP
260 1323 2032 /FPGA_Bank_1_2/TMDS_TX1_2_N TOP
260 1323 2089 /FPGA_Bank_1_2/TMDS_TX1_2_N TOP
260 1324 2176 /FPGA_Bank_1_2/TMDS_TX1_2_N TOP
260 2240 1464 /FPGA_Bank_1_2/TMDS_TX1_2_N TOP
261 1333 2032 /FPGA_Bank_1_2/TMDS_TX1_2_P TOP
261 1333 2089 /FPGA_Bank_1_2/TMDS_TX1_2_P TOP
261 1334 2176 /FPGA_Bank_1_2/TMDS_TX1_2_P TOP
261 2220 1464 /FPGA_Bank_1_2/TMDS_TX1_2_P TOP
262 1273 2032 /FPGA_Bank_1_2/TMDS_TX1_CEC TOP
262 1280 1998 /FPGA_Bank_1_2/TMDS_TX1_CEC BOTTOM
262 1323 1875 /FPGA_Bank_1_2/TMDS_TX1_CEC *.Cu
262 2210 1454 /FPGA_Bank_1_2/TMDS_TX1_CEC TOP
263 1278 2032 /FPGA_Bank_1_2/TMDS_TX1_CLK_N TOP
263 1278 2089 /FPGA_Bank_1_2/TMDS_TX1_CLK_N TOP
263 1279 2176 /FPGA_Bank_1_2/TMDS_TX1_CLK_N TOP
263 2240 1444 /FPGA_Bank_1_2/TMDS_TX1_CLK_N TOP
264 1288 2032 /FPGA_Bank_1_2/TMDS_TX1_CLK_P TOP
264 1288 2089 /FPGA_Bank_1_2/TMDS_TX1_CLK_P TOP
264 1289 2176 /FPGA_Bank_1_2/TMDS_TX1_CLK_P TOP
264 2220 1444 /FPGA_Bank_1_2/TMDS_TX1_CLK_P TOP
265 1258 2032 /FPGA_Bank_1_2/TMDS_TX1_HOT TOP
265 1303 1848 /FPGA_Bank_1_2/TMDS_TX1_HOT *.Cu
265 2240 1484 /FPGA_Bank_1_2/TMDS_TX1_HOT TOP
266 1268 2032 /FPGA_Bank_1_2/TMDS_TX1_SCL TOP
266 1268 2050 /FPGA_Bank_1_2/TMDS_TX1_SCL BOTTOM
266 1301 1875 /FPGA_Bank_1_2/TMDS_TX1_SCL *.Cu
266 2220 1484 /FPGA_Bank_1_2/TMDS_TX1_SCL TOP
267 1260 1998 /FPGA_Bank_1_2/TMDS_TX1_SDA BOTTOM
267 1263 2032 /FPGA_Bank_1_2/TMDS_TX1_SDA TOP
267 1323 1848 /FPGA_Bank_1_2/TMDS_TX1_SDA *.Cu
267 2220 1454 /FPGA_Bank_1_2/TMDS_TX1_SDA TOP
268 1527 2032 /FPGA_Bank_1_2/TMDS_TX2_0_N TOP
268 1527 2089 /FPGA_Bank_1_2/TMDS_TX2_0_N TOP
268 1527 2176 /FPGA_Bank_1_2/TMDS_TX2_0_N TOP
268 2240 1404 /FPGA_Bank_1_2/TMDS_TX2_0_N TOP
269 1537 2032 /FPGA_Bank_1_2/TMDS_TX2_0_P TOP
269 1537 2089 /FPGA_Bank_1_2/TMDS_TX2_0_P TOP
269 1537 2176 /FPGA_Bank_1_2/TMDS_TX2_0_P TOP
269 2220 1404 /FPGA_Bank_1_2/TMDS_TX2_0_P TOP
27 2189 1163 /DDR3/DDR0_DQ12 TOP
27 2210 1524 /DDR3/DDR0_DQ12 TOP
270 1542 2032 /FPGA_Bank_1_2/TMDS_TX2_1_N TOP
270 1542 2089 /FPGA_Bank_1_2/TMDS_TX2_1_N TOP
270 1542 2176 /FPGA_Bank_1_2/TMDS_TX2_1_N TOP
270 2240 1394 /FPGA_Bank_1_2/TMDS_TX2_1_N TOP
271 1552 2032 /FPGA_Bank_1_2/TMDS_TX2_1_P TOP
271 1552 2089 /FPGA_Bank_1_2/TMDS_TX2_1_P TOP
271 1552 2176 /FPGA_Bank_1_2/TMDS_TX2_1_P TOP
271 2230 1394 /FPGA_Bank_1_2/TMDS_TX2_1_P TOP
272 1557 2032 /FPGA_Bank_1_2/TMDS_TX2_2_N TOP
272 1557 2089 /FPGA_Bank_1_2/TMDS_TX2_2_N TOP
272 1557 2176 /FPGA_Bank_1_2/TMDS_TX2_2_N TOP
272 2190 1424 /FPGA_Bank_1_2/TMDS_TX2_2_N TOP
273 1567 2032 /FPGA_Bank_1_2/TMDS_TX2_2_P TOP
273 1567 2089 /FPGA_Bank_1_2/TMDS_TX2_2_P TOP
273 1567 2176 /FPGA_Bank_1_2/TMDS_TX2_2_P TOP
273 2190 1414 /FPGA_Bank_1_2/TMDS_TX2_2_P TOP
274 1507 2004 /FPGA_Bank_1_2/TMDS_TX2_CEC *.Cu
274 1507 2032 /FPGA_Bank_1_2/TMDS_TX2_CEC TOP
274 1596 2012 /FPGA_Bank_1_2/TMDS_TX2_CEC BOTTOM
274 2230 1374 /FPGA_Bank_1_2/TMDS_TX2_CEC TOP
275 1512 2032 /FPGA_Bank_1_2/TMDS_TX2_CLK_N TOP
275 1512 2089 /FPGA_Bank_1_2/TMDS_TX2_CLK_N TOP
275 1512 2176 /FPGA_Bank_1_2/TMDS_TX2_CLK_N TOP
275 2190 1434 /FPGA_Bank_1_2/TMDS_TX2_CLK_N TOP
276 1522 2032 /FPGA_Bank_1_2/TMDS_TX2_CLK_P TOP
276 1522 2089 /FPGA_Bank_1_2/TMDS_TX2_CLK_P TOP
276 1522 2176 /FPGA_Bank_1_2/TMDS_TX2_CLK_P TOP
276 2180 1434 /FPGA_Bank_1_2/TMDS_TX2_CLK_P TOP
277 1492 1993 /FPGA_Bank_1_2/TMDS_TX2_HOT *.Cu
277 1492 2032 /FPGA_Bank_1_2/TMDS_TX2_HOT TOP
277 2240 1374 /FPGA_Bank_1_2/TMDS_TX2_HOT TOP
278 1501 1968 /FPGA_Bank_1_2/TMDS_TX2_SCL *.Cu
278 1502 2032 /FPGA_Bank_1_2/TMDS_TX2_SCL TOP
278 1578 1972 /FPGA_Bank_1_2/TMDS_TX2_SCL BOTTOM
278 2220 1384 /FPGA_Bank_1_2/TMDS_TX2_SCL TOP
279 1476 1968 /FPGA_Bank_1_2/TMDS_TX2_SDA *.Cu
279 1497 2032 /FPGA_Bank_1_2/TMDS_TX2_SDA TOP
279 1600 1967 /FPGA_Bank_1_2/TMDS_TX2_SDA BOTTOM
279 2240 1384 /FPGA_Bank_1_2/TMDS_TX2_SDA TOP
28 2189 1123 /DDR3/DDR0_DQ13 TOP
28 2210 1544 /DDR3/DDR0_DQ13 TOP
280 1827 1014 /FPGA_Bank_1_2/USB_D0 TOP
280 2220 1414 /FPGA_Bank_1_2/USB_D0 TOP
281 1827 1009 /FPGA_Bank_1_2/USB_D1 TOP
281 2210 1414 /FPGA_Bank_1_2/USB_D1 TOP
282 1827 1004 /FPGA_Bank_1_2/USB_D2 TOP
282 2220 1374 /FPGA_Bank_1_2/USB_D2 TOP
283 1827 999 /FPGA_Bank_1_2/USB_D3 TOP
283 2210 1384 /FPGA_Bank_1_2/USB_D3 TOP
284 1827 994 /FPGA_Bank_1_2/USB_D4 TOP
284 2230 1414 /FPGA_Bank_1_2/USB_D4 TOP
285 1821 982 /FPGA_Bank_1_2/USB_D5 TOP
285 2240 1414 /FPGA_Bank_1_2/USB_D5 TOP
286 1816 982 /FPGA_Bank_1_2/USB_D6 TOP
286 2220 1394 /FPGA_Bank_1_2/USB_D6 TOP
287 1801 982 /FPGA_Bank_1_2/USB_D7 TOP
287 2210 1404 /FPGA_Bank_1_2/USB_D7 TOP
288 1816 1030 /FPGA_Bank_1_2/USB_DIR TOP
288 2210 1424 /FPGA_Bank_1_2/USB_DIR TOP
289 1827 1019 /FPGA_Bank_1_2/USB_NXT TOP
289 2200 1424 /FPGA_Bank_1_2/USB_NXT TOP
29 2181 1171 /DDR3/DDR0_DQ14 TOP
29 2220 1534 /DDR3/DDR0_DQ14 TOP
290 1791 1030 /FPGA_Bank_1_2/USB_REFCLK TOP
290 2220 1424 /FPGA_Bank_1_2/USB_REFCLK TOP
291 1796 1030 /FPGA_Bank_1_2/USB_RESETB TOP
291 2200 1384 /FPGA_Bank_1_2/USB_RESETB TOP
292 1806 1030 /FPGA_Bank_1_2/USB_STP TOP
292 2210 1374 /FPGA_Bank_1_2/USB_STP TOP
293 1970 1457 /FPGA_Bank_1_2/100MHz TOP
293 1994 1474 /FPGA_Bank_1_2/100MHz TOP
293 2240 1424 /FPGA_Bank_1_2/100MHz TOP
294 1976 1600 /FPGA_Power/DONE TOP
294 2240 1344 /FPGA_Power/DONE TOP
294 2287 2019 /FPGA_Power/DONE TOP
295 1982 1333 /FPGA_Power/PROG_B TOP
295 2021 1840 /FPGA_Power/PROG_B TOP
295 2181 2019 /FPGA_Power/PROG_B TOP
295 2240 1534 /FPGA_Power/PROG_B TOP
296 2151 1614 /FPGA_Power/RFS TOP
296 2160 1404 /FPGA_Power/RFS TOP
297 2088 1614 /FPGA_Power/SUSPEND TOP
297 2230 1334 /FPGA_Power/SUSPEND TOP
298 1955 673 /FPGA_Power/TCK TOP
298 2030 1344 /FPGA_Power/TCK TOP
298 2234 2019 /FPGA_Power/TCK TOP
299 1934 673 /FPGA_Power/TMS TOP
299 2060 1354 /FPGA_Power/TMS TOP
299 2216 2019 /FPGA_Power/TMS TOP
3 2109 1163 /DDR3/DDR0_A10 TOP
3 2110 1514 /DDR3/DDR0_A10 TOP
3 2141 1092 /DDR3/DDR0_A10 BOTTOM
30 2189 1131 /DDR3/DDR0_DQ15 TOP
30 2220 1544 /DDR3/DDR0_DQ15 TOP
300 2131 1614 /FPGA_Power/VBATT TOP
300 2180 1394 /FPGA_Power/VBATT TOP
301 2111 1614 /FPGA_Power/VFS TOP
301 2190 1384 /FPGA_Power/VFS TOP
302 2765 2071 /GPIOs/PRSNT *.Cu
302 2785 1761 /GPIOs/PRSNT *.Cu
302 2785 1901 /GPIOs/PRSNT *.Cu
302 2810 1581 /GPIOs/PRSNT *.Cu
303 1198 2008 /HDMI/HDMI-TX1-VCC5V0 BOTTOM
303 1198 2026 /HDMI/HDMI-TX1-VCC5V0 BOTTOM
303 1198 2049 /HDMI/HDMI-TX1-VCC5V0 BOTTOM
303 1198 2068 /HDMI/HDMI-TX1-VCC5V0 TOP
303 1249 2176 /HDMI/HDMI-TX1-VCC5V0 TOP
304 1406 2010 /HDMI/HDMI-TX2-VCC5V0 BOTTOM
304 1406 2030 /HDMI/HDMI-TX2-VCC5V0 BOTTOM
304 1406 2049 /HDMI/HDMI-TX2-VCC5V0 BOTTOM
304 1406 2068 /HDMI/HDMI-TX2-VCC5V0 TOP
304 1482 2176 /HDMI/HDMI-TX2-VCC5V0 TOP
305 1225 2118 /HDMI/HDMI_VCC5V0 TOP
305 1238 2118 /HDMI/HDMI_VCC5V0 TOP
305 1348 2032 /HDMI/HDMI_VCC5V0 TOP
305 1459 2118 /HDMI/HDMI_VCC5V0 TOP
305 1471 2118 /HDMI/HDMI_VCC5V0 TOP
305 1582 2032 /HDMI/HDMI_VCC5V0 TOP
305 1647 1873 /HDMI/HDMI_VCC5V0 BOTTOM
305 1647 1891 /HDMI/HDMI_VCC5V0 BOTTOM
305 1647 1909 /HDMI/HDMI_VCC5V0 BOTTOM
305 1647 1928 /HDMI/HDMI_VCC5V0 TOP
305 1667 2118 /HDMI/HDMI_VCC5V0 TOP
305 1692 2118 /HDMI/HDMI_VCC5V0 TOP
305 1705 2118 /HDMI/HDMI_VCC5V0 TOP
305 1816 2032 /HDMI/HDMI_VCC5V0 TOP
305 1901 2118 /HDMI/HDMI_VCC5V0 TOP
305 1926 2118 /HDMI/HDMI_VCC5V0 TOP
305 1939 2118 /HDMI/HDMI_VCC5V0 TOP
305 2050 2032 /HDMI/HDMI_VCC5V0 TOP
306 1952 2127 /HDMI/P1-CEC TOP
306 1975 2089 /HDMI/P1-CEC TOP
306 1975 2176 /HDMI/P1-CEC TOP
307 1901 2127 /HDMI/P1-HOT TOP
307 1913 2127 /HDMI/P1-HOT TOP
307 1945 2176 /HDMI/P1-HOT TOP
307 1960 2089 /HDMI/P1-HOT TOP
308 1939 2127 /HDMI/P1-SCL TOP
308 1965 2176 /HDMI/P1-SCL TOP
308 1970 2089 /HDMI/P1-SCL TOP
309 1926 2127 /HDMI/P1-SDA TOP
309 1960 2176 /HDMI/P1-SDA TOP
309 1965 2089 /HDMI/P1-SDA TOP
31 2149 1123 /DDR3/DDR0_DQ2 TOP
31 2160 1534 /DDR3/DDR0_DQ2 TOP
310 1251 2127 /HDMI/P2-CEC TOP
310 1273 2089 /HDMI/P2-CEC TOP
310 1274 2176 /HDMI/P2-CEC TOP
311 1212 2127 /HDMI/P2-HOT TOP
311 1244 2176 /HDMI/P2-HOT TOP
311 1258 2089 /HDMI/P2-HOT TOP
312 1238 2127 /HDMI/P2-SCL TOP
312 1264 2176 /HDMI/P2-SCL TOP
312 1268 2089 /HDMI/P2-SCL TOP
313 1225 2127 /HDMI/P2-SDA TOP
313 1259 2176 /HDMI/P2-SDA TOP
313 1263 2089 /HDMI/P2-SDA TOP
314 1718 2127 /HDMI/P3-CEC TOP
314 1741 2089 /HDMI/P3-CEC TOP
314 1741 2176 /HDMI/P3-CEC TOP
315 1667 2127 /HDMI/P3-HOT TOP
315 1680 2127 /HDMI/P3-HOT TOP
315 1711 2176 /HDMI/P3-HOT TOP
315 1726 2089 /HDMI/P3-HOT TOP
316 1705 2127 /HDMI/P3-SCL TOP
316 1731 2176 /HDMI/P3-SCL TOP
316 1736 2089 /HDMI/P3-SCL TOP
317 1692 2127 /HDMI/P3-SDA TOP
317 1726 2176 /HDMI/P3-SDA TOP
317 1731 2089 /HDMI/P3-SDA TOP
318 1484 2127 /HDMI/P4-CEC TOP
318 1507 2089 /HDMI/P4-CEC TOP
318 1507 2176 /HDMI/P4-CEC TOP
319 1446 2127 /HDMI/P4-HOT TOP
319 1477 2176 /HDMI/P4-HOT TOP
319 1492 2089 /HDMI/P4-HOT TOP
32 2149 1171 /DDR3/DDR0_DQ3 TOP
32 2160 1544 /DDR3/DDR0_DQ3 TOP
320 1471 2127 /HDMI/P4-SCL TOP
320 1497 2176 /HDMI/P4-SCL TOP
320 1502 2089 /HDMI/P4-SCL TOP
321 1459 2127 /HDMI/P4-SDA TOP
321 1492 2176 /HDMI/P4-SDA TOP
321 1497 2089 /HDMI/P4-SDA TOP
322 2501 760 /Power/Conference 12V
322 2550 990 /Power/Conference 12V
322 2574 865 /Power/Conference 12V
322 2588 990 /Power/Conference 12V
322 2612 865 /Power/Conference 12V
322 2626 990 /Power/Conference 12V
322 2784 1175 /Power/Conference 12V
322 2838 932 /Power/Conference 12V
323 2392 585 /Power/Consumer 12V
323 2446 799 /Power/Consumer 12V
323 2487 712 /Power/Consumer 12V
324 2555 604 /Power/VIN +48V
324 2705 586 /Power/VIN +48V
324 2719 785 /Power/VIN +48V
325 2504 604 /Power/VIN -48V
325 2669 785 /Power/VIN -48V
325 2705 646 /Power/VIN -48V
325 2752 616 /Power/VIN -48V
326 2652 1102 /Power/VIN 48
326 2652 1137 /Power/VIN 48
326 2652 1173 /Power/VIN 48
326 2680 1170 /Power/VIN 48
326 2742 1128 /Power/VIN 48
326 2769 785 /Power/VIN 48
326 2823 1194 /Power/VIN 48
326 2823 1234 /Power/VIN 48
327 1973 1671 /SPI_Flash/27MHz BOTTOM
327 2014 1725 /SPI_Flash/27MHz TOP
327 2150 1364 /SPI_Flash/27MHz TOP
328 2021 1881 /SPI_Flash/RST TOP
328 2059 1881 /SPI_Flash/RST TOP
328 2661 1282 /SPI_Flash/RST *.Cu
329 1975 673 /SPI_Flash/TDO-FPGA/TDO-JTAG TOP
329 2090 1384 /SPI_Flash/TDO-FPGA/TDO-JTAG TOP
329 2163 2019 /SPI_Flash/TDO-FPGA/TDO-JTAG TOP
33 2130 1524 /DDR3/DDR0_DQ4 TOP
33 2133 1131 /DDR3/DDR0_DQ4 TOP
330 1996 673 /SPI_Flash/TDO-USB/TDI-FPGA TOP
330 2070 1374 /SPI_Flash/TDO-USB/TDI-FPGA TOP
330 2199 2019 /SPI_Flash/TDO-USB/TDI-FPGA TOP
331 1746 894 /USB/CPEN TOP
331 1779 989 /USB/CPEN TOP
332 2152 2120 /USB/CYDN *.Cu
332 2170 2064 /USB/CYDN *.Cu
332 2298 1857 /USB/CYDN TOP
333 2145 2064 /USB/CYDP *.Cu
333 2152 2140 /USB/CYDP *.Cu
333 2298 1864 /USB/CYDP TOP
334 2059 1840 /USB/CYP-RESET TOP
334 2098 1943 /USB/CYP-RESET BOTTOM
334 2131 2012 /USB/CYP-RESET *.Cu
334 2135 1948 /USB/CYP-RESET TOP
335 1667 614 /USB/ID TOP
335 1779 1019 /USB/ID TOP
336 2298 1779 /USB/U1-SDA TOP
336 2336 1729 /USB/U1-SDA *.Cu
336 2341 1777 /USB/U1-SDA TOP
337 1687 614 /USB/USB_5V TOP
337 1717 997 /USB/USB_5V TOP
337 1750 694 /USB/USB_5V *.Cu
337 1751 901 /USB/USB_5V BOTTOM
337 1806 920 /USB/USB_5V TOP
337 1806 933 /USB/USB_5V TOP
338 1680 614 /USB/USB_DM TOP
338 1750 669 /USB/USB_DM *.Cu
338 1779 999 /USB/USB_DM TOP
339 1674 614 /USB/USB_DP TOP
339 1750 644 /USB/USB_DP *.Cu
339 1779 994 /USB/USB_DP TOP
34 2130 1544 /DDR3/DDR0_DQ5 TOP
34 2133 1171 /DDR3/DDR0_DQ5 TOP
340 2298 1903 /USB/XTALIN TOP
340 2379 1931 /USB/XTALIN *.Cu
340 2407 1880 /USB/XTALIN BOTTOM
341 2298 1909 /USB/XTALIOUT TOP
341 2379 1880 /USB/XTALIOUT *.Cu
341 2407 1931 /USB/XTALIOUT BOTTOM
342 1139 1211 GND 
342 1139 1268 GND 
342 1202 1029 GND TOP
342 1207 2249 GND *.Cu
342 1211 763 GND TOP
342 1212 2118 GND TOP
342 1213 2008 GND BOTTOM
342 1213 2026 GND BOTTOM
342 1213 2027 GND TOP
342 1213 2049 GND BOTTOM
342 1213 2068 GND TOP
342 1213 2189 GND *.Cu
342 1226 2049 GND BOTTOM
342 1228 956 GND TOP
342 1228 1029 GND TOP
342 1240 617 GND *.Cu
342 1240 1938 GND *.Cu
342 1241 833 GND TOP
342 1241 895 GND TOP
342 1247 1225 GND 
342 1253 956 GND TOP
342 1254 2176 GND TOP
342 1274 1194 GND 
342 1274 1661 GND BOTTOM
342 1275 1362 GND TOP
342 1277 763 GND TOP
342 1283 2032 GND TOP
342 1283 2089 GND TOP
342 1284 1328 GND 
342 1284 2176 GND TOP
342 1287 917 GND TOP
342 1291 640 GND TOP
342 1292 1661 GND TOP
342 1294 1029 GND TOP
342 1298 2032 GND TOP
342 1298 2089 GND TOP
342 1299 2176 GND TOP
342 1313 2032 GND TOP
342 1313 2089 GND TOP
342 1314 2176 GND TOP
342 1315 1661 GND BOTTOM
342 1319 1029 GND TOP
342 1328 2032 GND TOP
342 1328 2089 GND TOP
342 1329 2176 GND TOP
342 1335 871 GND TOP
342 1335 973 GND TOP
342 1338 2032 GND TOP
342 1338 2089 GND TOP
342 1339 711 GND *.Cu
342 1343 2118 GND TOP
342 1344 1029 GND TOP
342 1359 744 GND *.Cu
342 1361 2189 GND *.Cu
342 1367 2249 GND *.Cu
342 1371 1496 GND BOTTOM
342 1376 1532 GND TOP
342 1384 912 GND TOP
342 1384 948 GND TOP
342 1387 1265 GND *.Cu
342 1394 993 GND BOTTOM
342 1396 934 GND BOTTOM
342 1398 915 GND BOTTOM
342 1399 1578 GND TOP
342 1401 1631 GND TOP
342 1401 1672 GND TOP
342 1403 887 GND BOTTOM
342 1408 970 GND BOTTOM
342 1414 930 GND TOP
342 1421 2010 GND BOTTOM
342 1421 2027 GND TOP
342 1421 2030 GND BOTTOM
342 1421 2049 GND BOTTOM
342 1421 2068 GND TOP
342 1426 887 GND BOTTOM
342 1431 960 GND BOTTOM
342 1436 2049 GND BOTTOM
342 1441 2249 GND *.Cu
342 1446 2118 GND TOP
342 1447 2189 GND *.Cu
342 1454 934 GND BOTTOM
342 1465 1550 GND BOTTOM
342 1467 1573 GND BOTTOM
342 1470 952 GND BOTTOM
342 1480 1603 GND TOP
342 1485 1550 GND BOTTOM
342 1487 2176 GND TOP
342 1494 711 GND *.Cu
342 1495 948 GND TOP
342 1497 983 GND TOP
342 1497 1289 GND TOP
342 1505 1550 GND BOTTOM
342 1513 1360 GND BOTTOM
342 1517 2032 GND TOP
342 1517 2089 GND TOP
342 1517 2176 GND TOP
342 1520 1309 GND BOTTOM
342 1532 2032 GND TOP
342 1532 2089 GND TOP
342 1532 2176 GND TOP
342 1544 1298 GND TOP
342 1544 1304 GND TOP
342 1547 2032 GND TOP
342 1547 2089 GND TOP
342 1547 2176 GND TOP
342 1558 1398 GND BOTTOM
342 1562 2032 GND TOP
342 1562 2089 GND TOP
342 1562 2176 GND TOP
342 1563 670 GND TOP
342 1563 696 GND TOP
342 1563 762 GND TOP
342 1563 787 GND TOP
342 1563 813 GND TOP
342 1572 1218 GND BOTTOM
342 1572 2032 GND TOP
342 1572 2089 GND TOP
342 1573 1218 GND TOP
342 1573 1256 GND TOP
342 1573 1317 GND TOP
342 1577 2118 GND TOP
342 1581 955 GND BOTTOM
342 1582 904 GND BOTTOM
342 1595 2189 GND *.Cu
342 1601 2249 GND *.Cu
342 1602 1311 GND TOP
342 1638 586 GND *.Cu
342 1649 614 GND *.Cu
342 1650 1269 GND TOP
342 1661 614 GND TOP
342 1662 1873 GND BOTTOM
342 1662 1888 GND TOP
342 1662 1891 GND BOTTOM
342 1662 1909 GND BOTTOM
342 1662 1928 GND TOP
342 1674 2249 GND *.Cu
342 1675 1909 GND BOTTOM
342 1680 2118 GND TOP
342 1680 2189 GND *.Cu
342 1699 614 GND *.Cu
342 1710 586 GND *.Cu
342 1721 2176 GND TOP
342 1731 2200 GND BOTTOM
342 1737 1006 GND TOP
342 1750 618 GND *.Cu
342 1750 1009 GND BOTTOM
342 1751 2032 GND TOP
342 1751 2089 GND TOP
342 1751 2176 GND TOP
342 1755 1022 GND TOP
342 1766 901 GND BOTTOM
342 1766 2032 GND TOP
342 1766 2089 GND TOP
342 1766 2176 GND TOP
342 1781 2032 GND TOP
342 1781 2089 GND TOP
342 1781 2176 GND TOP
342 1791 1057 GND TOP
342 1793 894 GND BOTTOM
342 1795 998 GND TOP
342 1795 1015 GND TOP
342 1796 982 GND TOP
342 1796 2032 GND TOP
342 1796 2089 GND TOP
342 1796 2176 GND TOP
342 1806 907 GND TOP
342 1806 2032 GND TOP
342 1806 2089 GND TOP
342 1811 982 GND TOP
342 1811 1057 GND TOP
342 1811 2117 GND TOP
342 1812 998 GND TOP
342 1812 1015 GND TOP
342 1825 1044 GND BOTTOM
342 1827 989 GND TOP
342 1828 2189 GND *.Cu
342 1834 2249 GND *.Cu
342 1842 1028 GND BOTTOM
342 1889 625 GND *.Cu
342 1908 2249 GND *.Cu
342 1909 1246 GND *.Cu
342 1910 1519 GND BOTTOM
342 1913 2118 GND TOP
342 1914 2189 GND *.Cu
342 1915 625 GND *.Cu
342 1938 1725 GND TOP
342 1940 625 GND *.Cu
342 1955 2176 GND TOP
342 1961 1430 GND TOP
342 1965 2201 GND BOTTOM
342 1966 625 GND *.Cu
342 1970 1479 GND TOP
342 1972 1725 GND TOP
342 1985 2032 GND TOP
342 1985 2089 GND TOP
342 1985 2176 GND TOP
342 1988 1671 GND BOTTOM
342 1991 625 GND *.Cu
342 1994 1459 GND TOP
342 2000 2032 GND TOP
342 2000 2089 GND TOP
342 2000 2176 GND TOP
342 2015 1388 GND BOTTOM
342 2015 2032 GND TOP
342 2015 2089 GND TOP
342 2015 2176 GND TOP
342 2016 625 GND *.Cu
342 2018 1434 GND BOTTOM
342 2018 1479 GND BOTTOM
342 2025 1310 GND BOTTOM
342 2029 1362 GND BOTTOM
342 2030 1334 GND TOP
342 2030 1424 GND TOP
342 2030 1444 GND TOP
342 2030 1464 GND TOP
342 2030 1519 GND BOTTOM
342 2030 1544 GND TOP
342 2030 2032 GND TOP
342 2030 2089 GND TOP
342 2030 2176 GND TOP
342 2037 1613 GND TOP
342 2040 1384 GND TOP
342 2040 1404 GND TOP
342 2040 1444 GND TOP
342 2040 1484 GND TOP
342 2040 1504 GND TOP
342 2040 2032 GND TOP
342 2040 2089 GND TOP
342 2041 1409 GND BOTTOM
342 2042 625 GND *.Cu
342 2044 2118 GND TOP
342 2050 1172 GND TOP
342 2050 1394 GND TOP
342 2050 1414 GND TOP
342 2050 1434 GND TOP
342 2050 1474 GND TOP
342 2050 1494 GND TOP
342 2054 1109 GND TOP
342 2060 1394 GND TOP
342 2060 1454 GND TOP
342 2060 1494 GND TOP
342 2060 1613 GND TOP
342 2061 1435 GND BOTTOM
342 2061 1445 GND BOTTOM
342 2062 1489 GND BOTTOM
342 2062 2189 GND *.Cu
342 2068 2249 GND *.Cu
342 2069 1115 GND TOP
342 2069 1179 GND TOP
342 2069 1509 GND BOTTOM
342 2070 1344 GND TOP
342 2070 1404 GND TOP
342 2070 1414 GND TOP
342 2070 1444 GND TOP
342 2070 1484 GND TOP
342 2070 1534 GND TOP
342 2072 1204 GND TOP
342 2072 1317 GND BOTTOM
342 2079 1545 GND BOTTOM
342 2080 1424 GND TOP
342 2081 1340 GND BOTTOM
342 2081 1461 GND BOTTOM
342 2083 1088 GND TOP
342 2083 1943 GND BOTTOM
342 2085 1115 GND TOP
342 2085 1179 GND TOP
342 2086 1198 GND TOP
342 2088 1599 GND TOP
342 2090 1374 GND TOP
342 2090 1504 GND TOP
342 2096 1087 GND TOP
342 2099 1364 GND BOTTOM
342 2099 1441 GND BOTTOM
342 2100 1484 GND TOP
342 2101 1115 GND TOP
342 2101 1179 GND TOP
342 2103 1423 GND BOTTOM
342 2105 2167 GND *.Cu
342 2108 1190 GND BOTTOM
342 2109 1061 GND BOTTOM
342 2109 1380 GND BOTTOM
342 2110 1344 GND TOP
342 2110 1404 GND TOP
342 2110 1415 GND BOTTOM
342 2110 1424 GND TOP
342 2110 1444 GND TOP
342 2110 1464 GND TOP
342 2110 1466 GND BOTTOM
342 2110 1534 GND TOP
342 2111 1090 GND TOP
342 2113 1343 GND BOTTOM
342 2115 1445 GND BOTTOM
342 2118 1539 GND BOTTOM
342 2119 1061 GND BOTTOM
342 2119 2064 GND *.Cu
342 2120 1414 GND TOP
342 2120 1434 GND TOP
342 2120 1454 GND TOP
342 2121 1434 GND BOTTOM
342 2124 1144 GND BOTTOM
342 2125 1123 GND TOP
342 2125 1171 GND TOP
342 2125 1512 GND BOTTOM
342 2128 1334 GND BOTTOM
342 2129 1061 GND BOTTOM
342 2129 1092 GND TOP
342 2129 1127 GND BOTTOM
342 2129 1206 GND TOP
342 2129 1475 GND BOTTOM
342 2130 1374 GND TOP
342 2130 1424 GND TOP
342 2130 1435 GND BOTTOM
342 2130 1444 GND TOP
342 2130 1464 GND TOP
342 2130 1504 GND TOP
342 2133 1109 GND BOTTOM
342 2135 1870 GND TOP
342 2135 1935 GND TOP
342 2139 1061 GND BOTTOM
342 2139 1456 GND BOTTOM
342 2139 1771 GND BOTTOM
342 2140 1414 GND TOP
342 2140 1434 GND TOP
342 2140 1454 GND TOP
342 2141 1115 GND TOP
342 2141 1171 GND TOP
342 2141 1179 GND TOP
342 2141 1405 GND BOTTOM
342 2145 1175 GND BOTTOM
342 2148 1092 GND TOP
342 2149 1061 GND BOTTOM
342 2149 1179 GND TOP
342 2149 1387 GND BOTTOM
342 2150 1344 GND TOP
342 2150 1384 GND TOP
342 2150 1424 GND TOP
342 2150 1444 GND TOP
342 2150 1464 GND TOP
342 2150 1534 GND TOP
342 2151 1414 GND BOTTOM
342 2152 1455 GND BOTTOM
342 2155 1364 GND BOTTOM
342 2155 1544 GND BOTTOM
342 2155 1762 GND TOP
342 2156 1203 GND TOP
342 2157 1115 GND TOP
342 2157 1123 GND TOP
342 2157 1171 GND TOP
342 2159 1222 GND TOP
342 2160 1414 GND TOP
342 2160 1434 GND TOP
342 2160 1454 GND TOP
342 2161 758 GND TOP
342 2162 1061 GND BOTTOM
342 2164 1792 GND BOTTOM
342 2164 1955 GND BOTTOM
342 2165 1091 GND TOP
342 2165 1115 GND TOP
342 2165 1171 GND TOP
342 2165 1464 GND BOTTOM
342 2165 1504 GND BOTTOM
342 2165 1876 GND BOTTOM
342 2166 1375 GND BOTTOM
342 2168 1762 GND TOP
342 2170 1374 GND TOP
342 2170 1435 GND BOTTOM
342 2170 1504 GND TOP
342 2172 1061 GND BOTTOM
342 2172 1203 GND TOP
342 2173 653 GND *.Cu
342 2174 1393 GND BOTTOM
342 2176 1193 GND BOTTOM
342 2176 1546 GND BOTTOM
342 2178 1332 GND BOTTOM
342 2178 1424 GND BOTTOM
342 2178 1558 GND BOTTOM
342 2178 2140 GND *.Cu
342 2180 1085 GND TOP
342 2181 1115 GND TOP
342 2181 1131 GND TOP
342 2181 1179 GND TOP
342 2182 1061 GND BOTTOM
342 2189 1179 GND TOP
342 2189 1365 GND BOTTOM
342 2189 1976 GND BOTTOM
342 2190 1344 GND TOP
342 2190 1484 GND TOP
342 2190 1534 GND TOP
342 2192 1061 GND BOTTOM
342 2200 1204 GND TOP
342 2200 1414 GND TOP
342 2200 1454 GND TOP
342 2200 1514 GND TOP
342 2201 758 GND TOP
342 2204 1474 GND BOTTOM
342 2208 1061 GND BOTTOM
342 2210 1364 GND TOP
342 2210 1394 GND TOP
342 2210 1402 GND BOTTOM
342 2210 1484 GND TOP
342 2211 1434 GND BOTTOM
342 2213 1380 GND BOTTOM
342 2215 653 GND *.Cu
342 2215 900 GND TOP
342 2217 1492 GND BOTTOM
342 2218 1061 GND BOTTOM
342 2220 1466 GND BOTTOM
342 2221 1197 GND TOP
342 2225 2167 GND *.Cu
342 2226 1762 GND TOP
342 2226 2110 GND BOTTOM
342 2228 1061 GND BOTTOM
342 2228 1516 GND BOTTOM
342 2230 1384 GND TOP
342 2230 1424 GND TOP
342 2230 1464 GND TOP
342 2230 1466 GND BOTTOM
342 2230 1504 GND TOP
342 2232 1548 GND BOTTOM
342 2233 1425 GND BOTTOM
342 2233 1776 GND BOTTOM
342 2238 1061 GND BOTTOM
342 2239 1376 GND BOTTOM
342 2239 1985 GND TOP
342 2240 825 GND BOTTOM
342 2240 1334 GND TOP
342 2240 1340 GND BOTTOM
342 2240 1544 GND TOP
342 2244 1425 GND BOTTOM
342 2247 1453 GND BOTTOM
342 2248 1521 GND BOTTOM
342 2251 1061 GND BOTTOM
342 2257 653 GND *.Cu
342 2258 1474 GND BOTTOM
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342 2264 1314 GND BOTTOM
342 2265 1776 GND BOTTOM
342 2267 2072 GND TOP
342 2268 1844 GND BOTTOM
342 2268 1870 GND BOTTOM
342 2268 1916 GND BOTTOM
342 2270 896 GND TOP
342 2270 1100 GND BOTTOM
342 2270 1110 GND BOTTOM
342 2270 1120 GND BOTTOM
342 2270 1130 GND BOTTOM
342 2270 1140 GND BOTTOM
342 2270 1153 GND BOTTOM
342 2270 1163 GND BOTTOM
342 2270 1173 GND BOTTOM
342 2270 1183 GND BOTTOM
342 2272 1985 GND TOP
342 2273 1331 GND BOTTOM
342 2277 838 GND TOP
342 2277 1689 GND BOTTOM
342 2278 1201 GND BOTTOM
342 2278 1211 GND BOTTOM
342 2279 1388 GND TOP
342 2279 1398 GND TOP
342 2283 867 GND TOP
342 2283 1651 GND TOP
342 2283 1664 GND TOP
342 2283 1689 GND TOP
342 2287 2157 GND *.Cu
342 2287 2225 GND *.Cu
342 2294 2099 GND TOP
342 2298 1838 GND TOP
342 2298 1851 GND TOP
342 2298 1896 GND TOP
342 2298 1961 GND TOP
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342 2303 1984 GND BOTTOM
342 2316 798 GND TOP
342 2330 2122 GND BOTTOM
342 2334 2131 GND TOP
342 2337 920 GND TOP
342 2344 897 GND BOTTOM
342 2347 1461 GND TOP
342 2349 2131 GND TOP
342 2350 2122 GND BOTTOM
342 2354 2158 GND BOTTOM
342 2356 1813 GND TOP
342 2356 1831 GND TOP
342 2360 1242 GND *.Cu
342 2360 1293 GND *.Cu
342 2366 1082 GND BOTTOM
342 2366 1105 GND BOTTOM
342 2366 1130 GND TOP
342 2366 1150 GND TOP
342 2366 1151 GND BOTTOM
342 2366 1171 GND BOTTOM
342 2373 2122 GND BOTTOM
342 2374 2131 GND TOP
342 2385 897 GND TOP
342 2385 899 GND BOTTOM
342 2389 2131 GND TOP
342 2392 645 GND *.Cu
342 2396 1710 GND *.Cu
342 2404 2131 GND TOP
342 2407 1125 GND TOP
342 2411 1242 GND *.Cu
342 2411 1293 GND *.Cu
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342 2419 2131 GND TOP
342 2422 1880 GND BOTTOM
342 2422 1931 GND BOTTOM
342 2424 1125 GND TOP
342 2432 1086 GND TOP
342 2439 615 GND *.Cu
342 2440 989 GND TOP
342 2441 1120 GND TOP
342 2446 763 GND TOP
342 2452 2157 GND *.Cu
342 2452 2225 GND *.Cu
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342 2475 1242 GND *.Cu
342 2475 1293 GND *.Cu
342 2492 1099 GND TOP
342 2500 2086 GND TOP
342 2515 2157 GND *.Cu
342 2515 2225 GND *.Cu
342 2517 1842 GND *.Cu
342 2518 2086 GND TOP
342 2526 1242 GND *.Cu
342 2526 1293 GND *.Cu
342 2550 960 GND TOP
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342 2563 2131 GND TOP
342 2574 895 GND BOTTOM
342 2578 2131 GND TOP
342 2581 2127 GND BOTTOM
342 2588 960 GND TOP
342 2603 2127 GND BOTTOM
342 2603 2131 GND TOP
342 2612 895 GND BOTTOM
342 2618 2131 GND TOP
342 2619 785 GND *.Cu
342 2621 1102 GND TOP
342 2621 1137 GND TOP
342 2621 1173 GND TOP
342 2626 960 GND TOP
342 2633 2131 GND TOP
342 2637 1331 GND TOP
342 2648 2131 GND TOP
342 2677 1226 GND BOTTOM
342 2680 2157 GND *.Cu
342 2680 2225 GND *.Cu
342 2681 1036 GND TOP
342 2688 1128 GND TOP
342 2715 1122 GND TOP
342 2718 1165 GND TOP
342 2718 1186 GND TOP
342 2735 1175 GND TOP
342 2765 1611 GND *.Cu
342 2765 1751 GND *.Cu
342 2765 1771 GND *.Cu
342 2765 1811 GND *.Cu
342 2765 1851 GND *.Cu
342 2765 1911 GND *.Cu
342 2765 1951 GND *.Cu
342 2765 1991 GND *.Cu
342 2765 2031 GND *.Cu
342 2771 1130 GND TOP
342 2785 1641 GND *.Cu
342 2785 1721 GND *.Cu
342 2785 1801 GND *.Cu
342 2785 1841 GND *.Cu
342 2785 1881 GND *.Cu
342 2785 1941 GND *.Cu
342 2785 1981 GND *.Cu
342 2785 2021 GND *.Cu
342 2785 2061 GND *.Cu
342 2785 2081 GND *.Cu
342 2791 1130 GND TOP
342 2810 1741 GND *.Cu
342 2810 1821 GND *.Cu
342 2810 1861 GND *.Cu
342 2810 1901 GND *.Cu
342 2810 1961 GND *.Cu
342 2810 2001 GND *.Cu
342 2810 2041 GND *.Cu
342 2810 2081 GND *.Cu
342 2815 617 GND *.Cu
342 2815 2167 GND *.Cu
342 2830 1611 GND *.Cu
342 2830 1711 GND *.Cu
342 2830 1771 GND *.Cu
342 2830 1791 GND *.Cu
342 2830 1831 GND *.Cu
342 2830 1871 GND *.Cu
342 2830 1931 GND *.Cu
342 2830 1971 GND *.Cu
342 2830 2011 GND *.Cu
342 2830 2051 GND *.Cu
342 2854 1194 GND BOTTOM
342 2854 1234 GND TOP
343 2109 1171 N-00000178 TOP
343 2133 1144 N-00000178 BOTTOM
344 2109 1123 N-00000182 TOP
344 2167 1193 N-00000182 BOTTOM
345 1929 1600 N-00000189 TOP
345 1955 1600 N-00000189 TOP
346 1867 1557 N-00000192 BOTTOM
346 1910 1532 N-00000192 TOP
346 1962 1551 N-00000192 TOP
347 1867 1535 N-00000193 BOTTOM
347 1910 1545 N-00000193 TOP
347 1964 1526 N-00000193 TOP
348 1991 600 N-00000194 *.Cu
348 1996 688 N-00000194 TOP
349 1972 1674 N-00000195 TOP
349 2000 1759 N-00000195 TOP
35 2140 1534 /DDR3/DDR0_DQ6 TOP
35 2141 1123 /DDR3/DDR0_DQ6 TOP
350 1915 600 N-00000198 *.Cu
350 1934 688 N-00000198 TOP
351 1940 600 N-00000199 *.Cu
351 1955 688 N-00000199 TOP
352 1966 600 N-00000200 *.Cu
352 1975 688 N-00000200 TOP
353 2661 1257 N-00000202 *.Cu
353 2662 1226 N-00000202 BOTTOM
354 2636 1282 N-00000203 *.Cu
354 2637 1346 N-00000203 TOP
355 2585 1282 N-00000205 *.Cu
355 2609 1346 N-00000205 TOP
356 2573 1346 N-00000206 TOP
356 2585 1257 N-00000206 *.Cu
357 1919 1461 N-00000207 TOP
357 1945 1479 N-00000207 TOP
358 2298 1478 N-00000211 TOP
358 2347 1503 N-00000211 TOP
359 2306 1429 N-00000213 TOP
359 2385 1267 N-00000213 *.Cu
36 2133 1163 /DDR3/DDR0_DQ7 TOP
36 2140 1544 /DDR3/DDR0_DQ7 TOP
360 2299 1462 N-00000214 TOP
360 2372 1503 N-00000214 TOP
361 2318 1429 N-00000217 TOP
361 2501 1267 N-00000217 *.Cu
362 2040 1454 N-00000218 TOP
362 2282 1438 N-00000218 TOP
363 2070 1464 N-00000232 TOP
363 2203 1414 N-00000232 BOTTOM
364 2030 1454 N-00000233 TOP
364 2271 1438 N-00000233 TOP
365 2040 1310 N-00000235 BOTTOM
365 2170 1484 N-00000235 TOP
366 1339 1362 N-00000249 TOP
366 1884 1369 N-00000249 TOP
367 2398 1461 N-00000250 TOP
367 2425 1490 N-00000250 TOP
368 1408 960 N-00000251 TOP
368 1410 744 N-00000251 *.Cu
369 1384 744 N-00000254 *.Cu
369 1432 960 N-00000254 TOP
37 2165 1163 /DDR3/DDR0_DQ8 TOP
37 2180 1534 /DDR3/DDR0_DQ8 TOP
370 1416 960 N-00000255 TOP
370 1435 744 N-00000255 *.Cu
371 1420 960 N-00000256 TOP
371 1422 770 N-00000256 *.Cu
372 1397 770 N-00000257 *.Cu
372 1428 960 N-00000257 TOP
373 1384 916 N-00000258 TOP
373 1480 948 N-00000258 TOP
374 1392 960 N-00000259 TOP
374 1473 770 N-00000259 *.Cu
375 1400 900 N-00000260 TOP
375 1454 1006 N-00000260 TOP
376 1396 960 N-00000261 TOP
376 1460 744 N-00000261 *.Cu
377 1404 960 N-00000262 TOP
377 1448 770 N-00000262 *.Cu
378 1396 900 N-00000263 TOP
378 1482 983 N-00000263 TOP
379 1408 900 N-00000266 TOP
379 1434 1006 N-00000266 TOP
38 2173 1131 /DDR3/DDR0_DQ9 TOP
38 2180 1544 /DDR3/DDR0_DQ9 TOP
380 1213 930 N-00000268 TOP
380 1215 895 N-00000268 TOP
381 2476 1817 N-00000269 TOP
381 2517 1817 N-00000269 *.Cu
382 1266 895 N-00000271 TOP
382 1272 917 N-00000271 TOP
382 1272 937 N-00000271 TOP
383 1482 640 N-00000275 *.Cu
383 1516 640 N-00000275 TOP
384 2283 1676 N-00000279 TOP
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478 2109 1052 VTTDDR0 BOTTOM
478 2119 1052 VTTDDR0 BOTTOM
478 2125 1076 VTTDDR0 BOTTOM
478 2129 1052 VTTDDR0 BOTTOM
478 2133 1076 VTTDDR0 BOTTOM
478 2139 1052 VTTDDR0 BOTTOM
478 2141 1076 VTTDDR0 BOTTOM
478 2149 1052 VTTDDR0 BOTTOM
478 2149 1076 VTTDDR0 BOTTOM
478 2162 1052 VTTDDR0 BOTTOM
478 2167 1077 VTTDDR0 BOTTOM
478 2172 1052 VTTDDR0 BOTTOM
478 2175 1077 VTTDDR0 BOTTOM
478 2182 1052 VTTDDR0 BOTTOM
478 2183 1077 VTTDDR0 BOTTOM
478 2191 1077 VTTDDR0 BOTTOM
478 2192 1052 VTTDDR0 BOTTOM
478 2208 1052 VTTDDR0 BOTTOM
478 2212 1077 VTTDDR0 BOTTOM
478 2218 1052 VTTDDR0 BOTTOM
478 2220 1077 VTTDDR0 BOTTOM
478 2228 1052 VTTDDR0 BOTTOM
478 2228 1077 VTTDDR0 BOTTOM
478 2230 1156 VTTDDR0 BOTTOM
478 2230 1164 VTTDDR0 BOTTOM
478 2230 1172 VTTDDR0 BOTTOM
478 2230 1180 VTTDDR0 BOTTOM
478 2231 1114 VTTDDR0 BOTTOM
478 2231 1122 VTTDDR0 BOTTOM
478 2231 1130 VTTDDR0 BOTTOM
478 2231 1138 VTTDDR0 BOTTOM
478 2236 1077 VTTDDR0 BOTTOM
478 2238 1052 VTTDDR0 BOTTOM
478 2251 1052 VTTDDR0 BOTTOM
478 2256 1202 VTTDDR0 BOTTOM
478 2261 1100 VTTDDR0 BOTTOM
478 2261 1110 VTTDDR0 BOTTOM
478 2261 1120 VTTDDR0 BOTTOM
478 2261 1130 VTTDDR0 BOTTOM
478 2261 1140 VTTDDR0 BOTTOM
478 2261 1153 VTTDDR0 BOTTOM
478 2261 1163 VTTDDR0 BOTTOM
478 2261 1173 VTTDDR0 BOTTOM
478 2261 1183 VTTDDR0 BOTTOM
478 2269 1201 VTTDDR0 BOTTOM
478 2269 1211 VTTDDR0 BOTTOM
478 2385 1130 VTTDDR0 TOP
478 2385 1150 VTTDDR0 TOP
478 2385 1151 VTTDDR0 BOTTOM
478 2385 1171 VTTDDR0 BOTTOM
478 2441 1115 VTTDDR0 TOP
478 2441 1125 VTTDDR0 TOP
479 2040 1544 VTTREF TOP
479 2101 1171 VTTREF TOP
479 2120 1474 VTTREF TOP
479 2129 1215 VTTREF TOP
479 2133 1115 VTTREF TOP
479 2140 1474 VTTREF TOP
479 2160 1474 VTTREF TOP
479 2166 1366 VTTREF BOTTOM
479 2273 1340 VTTREF BOTTOM
479 2407 1115 VTTREF TOP
479 2467 1175 VTTREF TOP
48 2100 1534 /DDR3/DDR0_WE_N TOP
48 2109 1131 /DDR3/DDR0_WE_N TOP
48 2133 1092 /DDR3/DDR0_WE_N BOTTOM
49 2180 1444 /DisplayPort/DPRXAUXCH_N TOP
49 2190 1454 /DisplayPort/DPRXAUXCH_N TOP
49 2564 2073 /DisplayPort/DPRXAUXCH_N TOP
5 2080 1544 /DDR3/DDR0_A12 TOP
5 2093 1163 /DDR3/DDR0_A12 TOP
5 2175 1093 /DDR3/DDR0_A12 BOTTOM
50 2180 1454 /DisplayPort/DPRXAUXCH_P TOP
50 2574 2073 /DisplayPort/DPRXAUXCH_P TOP
51 2230 1474 /DisplayPort/DPRXCONFIG1 TOP
51 2593 2131 /DisplayPort/DPRXCONFIG1 TOP
51 2603 2142 /DisplayPort/DPRXCONFIG1 BOTTOM
52 2240 1474 /DisplayPort/DPRXCONFIG2 TOP
52 2581 2142 /DisplayPort/DPRXCONFIG2 BOTTOM
52 2588 2131 /DisplayPort/DPRXCONFIG2 TOP
53 2050 1404 /DisplayPort/DPRX_LANEN0 TOP
53 2600 2073 /DisplayPort/DPRX_LANEN0 TOP
54 2050 1424 /DisplayPort/DPRX_LANEN1 TOP
54 2620 2073 /DisplayPort/DPRX_LANEN1 TOP
55 2050 1464 /DisplayPort/DPRX_LANEN2 TOP
55 2641 2073 /DisplayPort/DPRX_LANEN2 TOP
56 2050 1484 /DisplayPort/DPRX_LANEN3 TOP
56 2661 2073 /DisplayPort/DPRX_LANEN3 TOP
57 2060 1404 /DisplayPort/DPRX_LANEP0 TOP
57 2590 2073 /DisplayPort/DPRX_LANEP0 TOP
58 2060 1424 /DisplayPort/DPRX_LANEP1 TOP
58 2610 2073 /DisplayPort/DPRX_LANEP1 TOP
59 2060 1464 /DisplayPort/DPRX_LANEP2 TOP
59 2630 2073 /DisplayPort/DPRX_LANEP2 TOP
6 2069 1131 /DDR3/DDR0_A13 TOP
6 2110 1494 /DDR3/DDR0_A13 TOP
6 2241 1202 /DDR3/DDR0_A13 BOTTOM
60 2060 1484 /DisplayPort/DPRX_LANEP3 TOP
60 2651 2073 /DisplayPort/DPRX_LANEP3 TOP
61 2190 1404 /DisplayPort/DPTXAUXCH_N TOP
61 2200 1404 /DisplayPort/DPTXAUXCH_N TOP
61 2338 2073 /DisplayPort/DPTXAUXCH_N TOP
62 2180 1404 /DisplayPort/DPTXAUXCH_P TOP
62 2190 1394 /DisplayPort/DPTXAUXCH_P TOP
62 2348 2073 /DisplayPort/DPTXAUXCH_P TOP
63 2200 1354 /DisplayPort/DPTXCONFIG1 TOP
63 2364 2131 /DisplayPort/DPTXCONFIG1 TOP
63 2373 2137 /DisplayPort/DPTXCONFIG1 BOTTOM
64 2240 1364 /DisplayPort/DPTXCONFIG2 TOP
64 2350 2137 /DisplayPort/DPTXCONFIG2 BOTTOM
64 2359 2131 /DisplayPort/DPTXCONFIG2 TOP
65 2030 1494 /DisplayPort/DPTX_LANEN0 TOP
65 2423 2073 /DisplayPort/DPTX_LANEN0 TOP
66 2030 1474 /DisplayPort/DPTX_LANEN1 TOP
66 2403 2073 /DisplayPort/DPTX_LANEN1 TOP
67 2030 1414 /DisplayPort/DPTX_LANEN2 TOP
67 2382 2073 /DisplayPort/DPTX_LANEN2 TOP
68 2030 1394 /DisplayPort/DPTX_LANEN3 TOP
68 2362 2073 /DisplayPort/DPTX_LANEN3 TOP
69 2040 1494 /DisplayPort/DPTX_LANEP0 TOP
69 2433 2073 /DisplayPort/DPTX_LANEP0 TOP
7 2069 1163 /DDR3/DDR0_A14 TOP
7 2100 1504 /DDR3/DDR0_A14 TOP
7 2228 1093 /DDR3/DDR0_A14 BOTTOM
70 2040 1474 /DisplayPort/DPTX_LANEP1 TOP
70 2413 2073 /DisplayPort/DPTX_LANEP1 TOP
71 2040 1414 /DisplayPort/DPTX_LANEP2 TOP
71 2393 2073 /DisplayPort/DPTX_LANEP2 TOP
72 2040 1394 /DisplayPort/DPTX_LANEP3 TOP
72 2372 2073 /DisplayPort/DPTX_LANEP3 TOP
73 1384 924 /Ethernet/AVDD3V3 TOP
73 1412 960 /Ethernet/AVDD3V3 TOP
73 1582 719 /Ethernet/AVDD3V3 TOP
73 1582 762 /Ethernet/AVDD3V3 TOP
73 1582 787 /Ethernet/AVDD3V3 TOP
73 1582 813 /Ethernet/AVDD3V3 TOP
74 1444 924 /Ethernet/ETH_INT_B TOP
74 2200 1464 /Ethernet/ETH_INT_B TOP
75 1416 900 /Ethernet/ETH_MDC TOP
75 2200 1484 /Ethernet/ETH_MDC TOP
76 1408 1013 /Ethernet/ETH_MDIO TOP
76 1412 900 /Ethernet/ETH_MDIO TOP
76 2180 1474 /Ethernet/ETH_MDIO TOP
77 1409 993 /Ethernet/ETH_RESET_B BOTTOM
77 1420 900 /Ethernet/ETH_RESET_B TOP
77 2190 1474 /Ethernet/ETH_RESET_B TOP
78 1350 973 /Ethernet/ETH_RXCLK TOP
78 1444 928 /Ethernet/ETH_RXCLK TOP
78 2230 1434 /Ethernet/ETH_RXCLK TOP
79 1350 871 /Ethernet/ETH_RXCTL TOP
79 1444 952 /Ethernet/ETH_RXCTL TOP
79 2190 1464 /Ethernet/ETH_RXCTL TOP
8 2085 1131 /DDR3/DDR0_A2 TOP
8 2120 1504 /DDR3/DDR0_A2 TOP
8 2247 1122 /DDR3/DDR0_A2 BOTTOM
80 1350 891 /Ethernet/ETH_RXD0 TOP
80 1444 948 /Ethernet/ETH_RXD0 TOP
80 2170 1464 /Ethernet/ETH_RXD0 TOP
81 1350 912 /Ethernet/ETH_RXD1 TOP
81 1444 940 /Ethernet/ETH_RXD1 TOP
81 2170 1474 /Ethernet/ETH_RXD1 TOP
82 1350 932 /Ethernet/ETH_RXD2 TOP
82 1444 936 /Ethernet/ETH_RXD2 TOP
82 2210 1494 /Ethernet/ETH_RXD2 TOP
83 1350 952 /Ethernet/ETH_RXD3 TOP
83 1444 932 /Ethernet/ETH_RXD3 TOP
83 2220 1494 /Ethernet/ETH_RXD3 TOP
84 1444 916 /Ethernet/ETH_TXCLK TOP
84 2240 1434 /Ethernet/ETH_TXCLK TOP
85 1428 900 /Ethernet/ETH_TXCTL TOP
85 2210 1474 /Ethernet/ETH_TXCTL TOP
86 1444 912 /Ethernet/ETH_TXD0 TOP
86 2210 1464 /Ethernet/ETH_TXD0 TOP
87 1444 908 /Ethernet/ETH_TXD1 TOP
87 2220 1474 /Ethernet/ETH_TXD1 TOP
88 1436 900 /Ethernet/ETH_TXD2 TOP
88 2230 1494 /Ethernet/ETH_TXD2 TOP
89 1432 900 /Ethernet/ETH_TXD3 TOP
89 2240 1494 /Ethernet/ETH_TXD3 TOP
9 2093 1123 /DDR3/DDR0_A3 TOP
9 2140 1494 /DDR3/DDR0_A3 TOP
9 2246 1180 /DDR3/DDR0_A3 BOTTOM
90 1253 762 /Ethernet/ETH_VCC1V0 TOP
90 1277 782 /Ethernet/ETH_VCC1V0 TOP
90 1384 920 /Ethernet/ETH_VCC1V0 TOP
90 1392 900 /Ethernet/ETH_VCC1V0 TOP
90 1400 960 /Ethernet/ETH_VCC1V0 TOP
90 1403 871 /Ethernet/ETH_VCC1V0 BOTTOM
90 1408 955 /Ethernet/ETH_VCC1V0 BOTTOM
90 1424 900 /Ethernet/ETH_VCC1V0 TOP
90 1424 960 /Ethernet/ETH_VCC1V0 TOP
90 1426 871 /Ethernet/ETH_VCC1V0 BOTTOM
90 1431 945 /Ethernet/ETH_VCC1V0 BOTTOM
90 1454 919 /Ethernet/ETH_VCC1V0 BOTTOM
91 1270 1029 /Ethernet/ETH_VCC3V3 TOP
91 1294 1048 /Ethernet/ETH_VCC3V3 TOP
91 1319 1048 /Ethernet/ETH_VCC3V3 TOP
91 1335 891 /Ethernet/ETH_VCC3V3 TOP
91 1335 912 /Ethernet/ETH_VCC3V3 TOP
91 1335 932 /Ethernet/ETH_VCC3V3 TOP
91 1335 952 /Ethernet/ETH_VCC3V3 TOP
91 1344 1048 /Ethernet/ETH_VCC3V3 TOP
91 1381 934 /Ethernet/ETH_VCC3V3 BOTTOM
91 1383 915 /Ethernet/ETH_VCC3V3 BOTTOM
91 1384 908 /Ethernet/ETH_VCC3V3 TOP
91 1393 1013 /Ethernet/ETH_VCC3V3 TOP
91 1444 920 /Ethernet/ETH_VCC3V3 TOP
91 1444 944 /Ethernet/ETH_VCC3V3 TOP
91 1455 952 /Ethernet/ETH_VCC3V3 BOTTOM
92 1457 640 /Ethernet/LED0 *.Cu
93 1375 640 /Ethernet/LED1 *.Cu
94 2090 1494 /Ethernet/MAC_SCL TOP
94 2298 1786 /Ethernet/MAC_SCL TOP
94 2341 1795 /Ethernet/MAC_SCL TOP
94 2347 1676 /Ethernet/MAC_SCL TOP
95 2050 1544 /Ethernet/MAC_SDA TOP
95 2347 1689 /Ethernet/MAC_SDA TOP
95 2361 1729 /Ethernet/MAC_SDA *.Cu
96 2347 1664 /Ethernet/MAC_WP TOP
96 2467 1817 /Ethernet/MAC_WP TOP
97 1211 782 /Ethernet/VCC1V0 TOP
97 1234 762 /Ethernet/VCC1V0 TOP
97 1253 895 /Ethernet/VCC1V0 TOP
97 1253 975 /Ethernet/VCC1V0 TOP
97 1287 937 /Ethernet/VCC1V0 TOP
98 1384 928 /Ethernet/XTAL1_50MHZ TOP
98 1535 904 /Ethernet/XTAL1_50MHZ *.Cu
98 1566 955 /Ethernet/XTAL1_50MHZ BOTTOM
99 1384 932 /Ethernet/XTAL2_50MHZ TOP
99 1535 955 /Ethernet/XTAL2_50MHZ *.Cu
99 1566 904 /Ethernet/XTAL2_50MHZ BOTTOM
