# //  ModelSim SE 5.8e Aug 28 2004 Linux 2.6.18-274.3.1.el5
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# Project file /home/user4/spring13/jz2492/Advanced_Digital/LoadStore_Design/CounterReg/test_CounterReg.mpf was not found.
# Unable to open project.
# Loading project testbench_regCounterReg
# Compile of LS_regCounterReg.v was successful.
# Compile of testbench_LS_regCounterReg.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim -t ns work.testbench_LS_regCounterReg
# vsim -t ns work.testbench_LS_regCounterReg 
# Loading work.testbench_LS_regCounterReg
# Loading work.LS_regCounterReg
# ** Warning: (vsim-3009) [TSCALE] - Module 'LS_regCounterReg' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench_LS_regCounterReg/TEST
# ** Warning: (vsim-3017) /home/user4/spring13/jz2492/Advanced_Digital/LoadStore_Design/regCounterReg/testbench_LS_regCounterReg.v(12): [TFMPC] - Too few port connections. Expected 6, found 4.
#         Region: /testbench_LS_regCounterReg/TEST
# ** Warning: (vsim-3015) /home/user4/spring13/jz2492/Advanced_Digital/LoadStore_Design/regCounterReg/testbench_LS_regCounterReg.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (5) for port 'load'.
#         Region: /testbench_LS_regCounterReg/TEST
# ** Warning: (vsim-3722) /home/user4/spring13/jz2492/Advanced_Digital/LoadStore_Design/regCounterReg/testbench_LS_regCounterReg.v(12): [TFMPC] - Missing connection for port 'count'.
# ** Warning: (vsim-3722) /home/user4/spring13/jz2492/Advanced_Digital/LoadStore_Design/regCounterReg/testbench_LS_regCounterReg.v(12): [TFMPC] - Missing connection for port 'load_data'.
run
run
run
# Compile of LS_regCounterReg.v was successful.
# Compile of testbench_LS_regCounterReg.v was successful.
# 2 compiles, 0 failed with no errors. 
restart
# Loading work.testbench_LS_regCounterReg
# Loading work.LS_regCounterReg
# ** Warning: (vsim-3009) [TSCALE] - Module 'LS_regCounterReg' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench_LS_regCounterReg/TEST
run
run
