CS 6831 04f
HW 11   Due 12/8/04

READ Section 1-3 of Building Block paper (handed out in class).

IN TEXT 6.56 (implement C-element)

NT-1. Write SOP logic expressions for a 2-1 MUX that operates in
the world of dual-rail signals.  Data inputs are A and B (each
dual-railed), and the select signal S, is also dual-railed, as is the
output Z.  If S is undefined (S1 = S0 = 0), then Z should be
undefined.

NT-2. In the flow table of Fig. 3.4 of the Building Block paper
(a)  For the transition 1-1000->4-1001 there is a transient essential
hazard (TEH).  What output signal is involved?  Identify the term in
the logic expressions given for the table that may generate the glitch
for this transition.
(b)  Repeat the above for the transition 4-1000->3-1100.
(above 2 from hw9 02s)

NT-3. Draw ckt for one stage of the dual-rail adder that we discussed
in class.  As components use NAND's, NOR's and INVERTERS.  Try to
minimize # of gate-inputs.  I have a solution with 16 2-input gates
and 2 inverters, with maximum logic depth of 4-stages (depth of 2 for
generating the carry signals).

NT-4.  Consider the following sequential circuit.  There is a pullup
circuit consisting of 2 PMOS transistors in series, and a pulldown
circuit consisting of 2 NMOS transistors in series.  (i.e., there is a
chain of 4 transistors from Vdd to ground, the top two being PMOS and
the bottom two being NMOS).  The inputs to the
gates of the top PMOS and NMOS transistors are A, and the inputs to the
gates of the bottom PMOS and NMOS transistors are B.  On the path from
the junction of the lower PMOS and upper NMOS transistors is an
inverter whose output is the output, Z, of the overall circuit.
Finally, there is a small inverter feeding back from the Z to the
input of the other inverter.  Draw the circuit and figure out what it
does.