CS E6831 Solutions for HW #9
TEXT: 6/(56, 57)
<PRE>
6.56.  Implement a C-element with NOR-gates.

We can do this by finding a POS expression, which can then be
implemented by a 2-stage circuit consisting of only NOR-gates (this is
exactly equivalent to a 2-stage OR-AND circuit with the same inputs.)

The C-element flow table is given on p. 249: The state assignment is
added below

               AB
     00     01    11     10    y
1  (1),0  (1),0   2,0   (1),0  0
2   1,1   (2),1  (2),1  (2),1  1

A K-map for Y' is:
         C
    1 1 0 1
    1 0 0 0 y
       D      Y'

So we have Y' = C'D' + A'y' + D'y'
Using DeMorgan's Law we get Y = (C+D)(C+y)(D+y)
So the first stage consists of 3 2-input NOR-gates, with input pairs,
(C, D), (C, y), and (D, y).  The second stage NOR-gate is fed by the
outputs of these 3-gates.  Its output is labeled Y and is fed back to
the inputs as y.  Also, the output of the C-element is y, since it is
evident from the table that Z = y.

6.57. Construct a 4-input C-element using a 2-input C-element and some
other logic.

A 4-input C-element is a circuit whose output is 0 if all inputs are
0, and 1 if all inputs are 1.  The output changes only when ALL inputs
are the same.  So, once the output is 0, it can change to 1 only when
ALL inputs are 1, and once the output is 1, it can change to 0 only
when ALL inputs go to 0.

Suppose we feed all 4 inputs both to an AND-gate and to an OR-gate.
Then the outputs of both of these gates will be 0 if ALL 4 inputs are
0, and the outputs of both of these gates will be 1 if ALL 4 inputs
are 1.  So, if we feed the outputs of the AND-gate to one input of the
C-element and the outputs of the OR-gate to the other input of the
C-element, the C-element will change states only when all 4 inputs are
the same (0 or 1).  This is exactly what is needed to implement the
4-input C-element.

NT-1 Find logic expressions for a dual-rail 2-1 MUX.  Assume that when
S=0, the A-input is to be chosen, and when S=1, the B-input is to be
chosen.

Z1 = A1S0 + B1S1  Z0 = A0S0 + B0S1

NT-2. (a) Transient essential hazard for 1-1000->4-1001.  Note that
the second output variable, Rp is supposed to be constant at 0 in all
the states involved in the transition.  But, if the transition APPEARS
to involve  a change in y1 and THEN the change in input X1, 4-1000 will
appear to be an intermediate state, and Rp=1 in that state.  So Rp
would glitch to 1 during the transition if the hazard is manifested.
Rp = RsX1'y1y2'.  During the transition, since Rs is fixed at 1 and y2
is fixed at 0, the expression for Rp reduces to X1'y1.  Both in the
initial and in the final states X1' and y1 have opposite values, so Rp
starts and ends at 0.  But X1' is falling and y1 is rising, so we have
inputs to an AND-gate changing in opposite directions.  This will
result in a transient 1-pulse output if the variable going to 1
changes first.  In this case, if the operation goes as specified in
the flow table, X1' will change first (to 0), which would result in
correct operation.  But if the delays are unfortunately distributed,
it might appear that y1 goes ON before X1' goes off, in which case the
essential hazard is manifested.

(b) Repeat the above for the transition 4-1000->3-1100. 

Now, the output that might glitch is As, which is 0 in all states
involved, but which is 1 for the state reached if the internal
variable change appears to precede the input change that caused it.
That is, a change in input Ap initiates the action, and is followed by
a change in y2.  But, if y2 appears at the As terminal to have
changed first, then the y2 component of the product term for As will
go on BEFORE the Ap' term goes off, which causes a positive glitch at
the output of the AND-gate implementing As = X0'Ap'y2.

NT-4.   
(a) The maximum delay from an input to an output of the logic circuit
is on the path from S to Q  This delay is 3+3 = 6.  The shortest delay
is on the path from R to Q.  It can be as small as 2.  So we have
DLM=6, and DLm=2.

(b) The key is to find the longest possible dwell time in the
transient state 1-10.  This is the maximum difference between the time
an R-change takes to get thru and the time it might take an S-change
to get thru, assuming that the S-change starts as late as allowed
after the R-change.  The R-change might get thru with delay 2.  The
S-change could take as long as 3+3 = 6 to get thru and might start 1
unit of time after the R-change.  So if the R-change starts at t=0, it
could arrive at t=2, while the S-change could arrive as late as t =
6+1 = 7.  Then the worst-case dwell time is 7-2 = 5.  We would need an
ID significantly greater than 5 to protect against a failure.

(c) If DEm = 5 and the tolerance is 0.1, then DEM = DEm(1+t)/(1-t) =
    5(1.1)(0.9) = 55/9 = 6.11.  Then to ensure that the changes appear
    to be serial,we need a minimal spacing of 2DLM+DEM-DLm =
    2x6+6.11-2 = 16.11
.............
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