CS E6831 02s
Solutions for HWK #8
Text: 6.26. For the transition starting with Q=0 and CD changing from
11 to 01, a sufficiently large delay in the path from C to the second
latch will cause Q to change to 1, because the second latch will
remain sensitive to its D-input, which will change when the first latch
changes state as a result of its C-input changing to 1. This is the
manifestation of a steady state essential hazard for this transition.
The same delay will cause similar malfunction when Q=1m D=0, and C
changes from 1 to 0.
Text 6.29. The circuit is described by the tables f Fig. 6.32.
There are essential hazards for transitions from 4-01 and from 7-00,
in both cases when X1 is turned on. Consider first the transition
form 4-01. Trouble occurs if the direct effect of the X1 change does
not reach Y3 until AFTER the change in y2, CAUSED by the X1 change,
reaches Y3. In that event, y3 will also change, leading the system
to the wrong state. A large stray delay in the X1-input to the
NOR-gate generating Y3 will cause this situation to occur.
For the transition from 7-00, the situation is reversed in that y3 is
SUPPOSED to change as a direct result of the X1-change, and a
malfunction will occur if the change in y3 reaches Y2 before the
signal from X1. Thus the malfunction can be made to occur by a large
delay at the X1-input to the gate producing Y2.
In the 4-01 case, the path from X1 to Y3 via y2 passes thru just two
gates, whereas in the 7-00 case, the trouble-producing path from X1 thru
y3 to Y2 passes thru 4 gates. Thus the likelihood of trouble is
significantly grater for the 4-01 case. Placing a sufficiently large
delay element at the output of the gate generating Y2, or in the path
from y2 to the input to the gate generating Y3 ensures against the
occurrence of this particular malfunction.
Text: 6-52. (a) A negative runt pulse on B starting in 2-01. The
problem is caused by having the B-signal change a second time before
the transition from state-2 to state-1 in the 00-column goes to
completion. Similar situations apply for a negative runt pulse on A
from 2-10, for a positive runt pulse on B from 1-10, and for a
positive runt pulse on A from 1-01.
(b) Multiple input changes terminating in either of the columns with
two stable states can lead to metastable behavior. These are from
1-01, 2-01, 1-10, and 2-10.
Text: 6-53. The entries in the 00-column could BOTH be stable, or
could both have next-state entries 2. In both cases the outputs would
remain 00. With these variations, it can be seen that the behavior
wold be exactly the same for isolated requests in the form of inputs 01
or 10. Simultaneous requests would result in the same dilemma.
ASYNC: 4.11. We consider only SIC operation. The steady state
essential hazards are listed below, each specified by the initial total
state and the input variable that changes.
2-01 x1, 4-00 x2, 4-00 x1
NT-1. The dynamic hazard is for a change in A when B=1, C=0, D=1, E=0.
With these values, the expression is reduced to AA'+A. To defeat the
hazards for A-changes in both directions, we can make the delay in the
path from A' to Z larger than the delays in both of the paths from A
to Z. (A similar result can be achieved by making the delay in the
path from A' to Z smaller than the delays in both of the paths from A
to Z.)
NT-1 (SECOND!). Identify all essential hazards, both transient and
steady-state, in flow table P4.13 on p. 189 of ASYNC. Consider
only SIC operation.
Steady-state: 2-10 x2, 2-10 x1, 3-11 x2, 4-01 x1,
Transient: 1-11 x1,
NT-2. (a) Find DM/Dm, given that tolerance is +-t
Average value, D = (DM+Dm)/2
(1) (DM-Dm)/D = 2t
(2) 2t = (DM-Dm)/((DM+Dm)/2) = 2(DM-Dm)/(DM+Dm)
(3) DMt+Dmt = DM-Dm
(4) DM-DMt = Dm+Dmt
(5) DM(1-t) = Dm(1+t)
(6) DM/Dm = (1+t)/(1-t)
(b) From step 2 above, dividing both sides by 2 yields:
t = (DM-Dm)/(DM+Dm)
NT-3. For n-step transitions, the maximum time to complete all signal
passages is: DLM + n(DLM + DEM). So, to ensure that all results of
the first input change reach all logic outputs before any results of
the second input change, we need a minimum spacing between changes
of: n(DLM + DEM) + DLM -DLm.
NT-4. Consider the circuit on p. 189 in the text (Fig. 6.31), and the
associated information about this circuit on the following
page. Assume there is a delay ranging between 2 and 3 units at
each input to each gate. These account for both gate and wiring
delays. Find DLM and DLm for the circuit.
The largest number gates in any path from an X or a y to a y or Z
(WITHOUT passing thru any other y's) is 3, in the path X2 to y2 (First
thru the lowest gate, then thru the top two gates). If we assume
maximum delays for each part of this path, then the longest delay thru
the logic is 3x3 = 9, so DLM = 9. There are 2 paths of length 1 from
X1 to a y, and other length-1 paths from y2 to y1, from y1 to Z2, and
from y3 to Z2. Since there may a minimum delay along at least one of
these paths, it is clear that DLm = 2
NT-5. For the circuit of problem 4, use the results you derived
(WITHOUT considering the detailed circuit paths) to compute DEm, the
minimum value of the delay elements in the feedback paths that would
ensure against the manifestation of any essential hazards. Assuming
delay tolerances of .2, use the results of problem 1 to compute DEM.
DEm = DLM-2DLm = 9-2x2 = 9-4 = 5
DEM = (DEM/DEm)(DEm) = ((1+t)/(1-t))DEm (1.2/0.8)(5) = 7.5
T-6. Continuing the discussion of the same circuit, find the minimum
allowable spacing between consecutive input changes.
An examination of Fig. 6.32b in the text indicates that some of the
transitions in the circuit under consideration are 2-step. These are
from 1-11 when X1 is changed (first y3 changes, then y1 changes), and
from 8-10 when X1 changes; first y2 changes, then y1 changes. We saw
in problem NT-3 that the spacing necessary for n-step transitions is
n(DLM + DEM) + DLM -DLm. So, with n = 2, and for the numbers
calculated for the present circuit, we can see that the minimum
spacing is 2(9+7.5)+9-2 = 40.
Note that this computation is based on the results of NT-5, where we
did NOT consider the detailed paths involved in the essential hazards.
Rather, we simply assumed that the extreme values of DL applied, in
the worst ways to the paths involved in the hazard. This leads us to
a very conservative, often overly pessimistic result. If we examine
the two essential hazards for the circuit, we can see that, even under
worst-case assumptions, they cannot be manifested even if DEm is set
to ), i.e., if we don't use ANY delay element. This of course makes
DEM 0, and so our above computation indicates that a spacing of 25
between consecutive input changes is safe under worst-case conditions.
But even this is overly conservative. A detailed examination of the
operation of this circuit, using the circuit diagram and the complete
flow matrix of Fig. 6.32b indicates that no transition leads to a
chain of gate output changes of length longer than 3 (and there are
transitions of that length). Therefore, if we maintain a minimum
spacing of 7, it will not be possible for the effects of any input
change to "overtake" the effects of the previous change. It is clear
then that detailed examinations of circuit paths can show us that
circuits can be operated at rates much greater than those calculated
on a crude worst-case basis.
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