COMS E6831  Sequential Logic Circuits
Solutions for HW #12

NT-1 Complete design of pulse-mode join element.

The flow matrix is:

                 AB
      00     01      11      10    y1 y2
1   (1),0    4,0     3,-     2,0    0  0
2   (2),0    3,-     3,-    (2),0   0  1
3    1,-    (3),1   (3),1   (3),1   1  1
4   (4),0   (4),0    3,-     3,-    1  0

Y1 = B + Ay1 + y1y2',    Y2 = A + By2 + y1'y2,   Z = y1y2
Y1 = B + (A + y2')y1,    Y2 = A + (B + y1')y2

Using the pullup-pulldown approach for  Y1 and Y2, we can obtain,
directly from the flow matrix, the following expressions:
Y1'+ = A'B'y2,   Y1'- = B,  Y2'+ = A'B'y1,  Y2'- = A

                        ___ Vdd
                         |
                     A-o|
                         |
                     B-o|
                         |
      ----------------------------------------
      |                                      |
       |o--------------    ----------------o|
      |                \  /                  |
      |                 \/                   |
      |                 /\                   |
      |   -------------/  \---------------   |
      |   |                               |  |
      |   .-o<|---             --|>o-------  |
      |y1'|      |y1        y2 |          |  |
      |---.-|>o--.             --0<|---------|
      |   |  ----|-------------|         y2' |
      |   |  |   |                           |
      |   |  _   |                            |--A 
  B--|    | \ /  |                           |
      |   .-o\---                            |
      |   | /_\                              |
      |   |  |                               |
      |   |  .-------------------------------|----------->Z
      |   |  |                               |
      |   --|                                |
      |      |                               |
      ------------------.---------------------
                        |
                        -
                        V (ground)

Note that Z = y1y2 is realized above by an AND-gate constructed using
a transmission gate (see text, p. 313 if you are not familiar with
transmission gates).  This is particularly economical because y1' is
available at no extra cost.

NT-2. Construct flow table for 4-phase to 2-phase converter.
Assume the 4-phase signals are R and A, and that the 2-phase signals
are S and F.  The primitive flow table is:

                RF
      00     01     11    10
1   (1),0     -      -    2,0
2      -      -    3,1-  (2),10
3      -    4,1-  (3),11    -
4      -   (4),10  5,-0     -
5      -      -   (5),00  6,0-
6    1,0-     -      -   (6),01
                                SA

It is obvious that this can be reduced to two rows by merging 123 and
456, as below.

                         RF
           00       01         11       10
(123) 1  (1),00    2,1,1-    (1),11   (1),10
(456) 2   1,0-    (2),10     (2),00   (2),01
                                        SA

NT-3. 
(a) There is a critical race from 1-11 to 3-11, i.e., in th 11-column
from row-1 to row-3.  There is another critical race from 2-10 to
4-10.

(b) K-maps for Y1 and Y2 are below

         A                B
    0 0 1 0          0 1 1 0

    0 0 0 1          1 1 1 0
  y2               y2
    0 1 1 1          1 1 1 1 
           y1               y1
    0 1 1 1          0 0 0 0
       B    Y1          B    Y2

From these we obtain: Y1 = ABy2' + Ay1 + By1 + AB'y2, and
 Y2 = A'y2 + By2 + By1' + y1y2

(c) For the critical race in column 11, we want to delay the paths from
y2 to Y1 and from y1 to Y2.  This would be achieved by delaying the
y2' input to the ABy2' AND-gate in the Y1-expression, and the y1'
input to the By1' AND-gate in the Y2 expression.

NT-4. Generating the pullup and pulldown expressions is best done by
inspection of the K-maps.
Y1'+ = A'B',   Y1'- = ABy2' + AB'y2
Y2'+ = AB'y1',   Y2'- = By1'

The pullup circuit for Y1' has 2 pMOS transistors in series, one fed
by A and the other by B.  The pulldown for Y1' has two parallel paths,
each with 3 pMOS transistors in series.  One path has transistors
controlled by A, B, and y2'.  The other has transistors fed by A, B',
and y2.

The pullup circuit for Y2' consists of 3 transistors in series,
controlled by A', B, and y1.  The Y2 pulldown circuit consists of 2
transistors in series, controlled by B and y1'.

In order to defeat the critical races, we need to slow down (most
conveniently by narrowing their channels) the y2' and y2 transistors
in the pulldown circuit for Y1, and the y1' transistors appearing in
the pullup and pulldown circuits for Y2.

NT-5.  A pulse-mode IF-box can be implemented by the following, very
simple combinational logic circuit: Rx = Rs, Rp = X1, As = X0 + Ap

NT-6. Below is a primitive flow table for a box converting from
pulse-mode to 4-phase handshakes.  (The pulse-mode signals are S and
F.)  Note that the R-signal is turned on following the LEADING edge of
the S-pulse.  WE might instead choose to wait for the trailing edge
before turning on R.

                 SA
      00      01    11     10
1   (1),00     -     -    2,-0
2    3,10      -     -   (2),10
3   (3),10    4,-0   -      -
4    1,01    (4),00  -      -
                                  RF

The multiple output-change occurs during the transition from 4-01 to
1-00, when, as a result of Ap going from 1 to 0, F changes from 0 to 1
to 0.  The duration of the F-pulse is determined by the time it takes
for the system to change from state-4 to state-1.

NT-7.  Following is a primitive flow table for a box converting
4-phase handshakes to pulse-mode handshakes.  Here, the A-signal is
turned on following the LEADING edge of the F-pulse.  Again, we might
have chosen to wait for the trailing edge.

                RF
      00     01    11      10
1   (1),00    -     -     2,10
2      -      -    3,0-  (2),00
3      -      -   (3),01  4,01
4    1,0-     -     -    (4),01
                                 SA