CS E6831 02s
HWK #11 Solutions
Text: 6.56
Starting with the flow table on p. 249, assigning y=0 to row-1 and y=1
to row-2, we obtain the K-map below for Y
A
0 0 1 0
0 1 1 1 y
B Y = AB + By + Ay Also, Q = y
The Y-expression above corresponds to a 2-stage AND-OR circuit, which,
in turn corresponds to a 2-stage NAND-gate circuit. To get an
implementation using NOR-gates, we need a product of sums expression
for the same function. This can be found by complementing the
Y-expression, multiplying it out, then complementing again, as below:
Y' = (A' + B')(B' + y')(A' + y') = A'B' + A'y' + B'y'
Y = (A + B)(A + y)(B + y).
So we have a 2-stage OR-AND, circuit, which corresponds to a 2-stage
NOR circuit.
Text: 6.57
Feed A, B, C, and D both to an AND-gate and to an OR-gate. Send the
outputs of these gates to the inputs of a C-element. If, initially,
all inputs are 0, then the inputs to the C-element will both be 0 and
the output will therefore go to (or remain) 0. The C-element output
can change to 1 only if both its inputs become 1, which can happen
only if A, B, C, and D all go to 1.
NT-1.
RsX1X0Ap
0000 1000 1010 1100 1001
1 (1),000 2,0"00
2 (2),100 3,1"00 5,1"00
3 4,000" (3),000
4 1,000" (4),001
5 6,00"0 (5),000
6 (6)010 7,01"0
7 4,000" (7),000
RxRpAs
NT-2. We can see by inspection that the rows can be merged into 3
sets of compatibles, 12, 347, 56. This leads to the table
below:
RsX1X0Ap
0000 1000 1010 1100 1001
(12) 1 (1),000 (1),100 2,000 3,100 -
(347) 2 1,001 (2),001 (2),000 - (2),000
(56) 3 - (3),000 - (3),000 2,010
RxRpAs
NT-3 The primitive flow table for the IF with single-rail X is:
RsXAp
000 001 011 010 110 111 101 100
1 (1),00 - - 3,00 - - - 2,0
2 1,0- - - - - - - (2),01
3 1,00 - - (3),00 4,-0 - - -
4 - - - - (4),10 5,-0 - -
5 - - - - 6,0- (5),00 - -
6 - - - 3,0- (6),01 - - -
RpAs
To reduced table is found by merging 124 and 56 as below
RsXAp
000 001 011 010 110 111 101 100
(1234) 1 (1),00 - - (1),00 (1),10 2,-0 - (1),01
(56) 2 - - - 1,0- (2),01 (2),00 - -
RpAs
Assigning y=0 to row-1 and y=1 to row-2, we get the following K-map
(in a stretched out form)
Ap Ap
Rs
0 - - 0 0 1 - 0 0 - - 0 1 - - 0 0 - - 0 0 0 - 1
- - - 0 1 1 - 1 y - - - 0 0 0 - - - - - - 1 0 - -
X Y Rp AS
This leads to Y = XAp + Rsy
Rp = RsXy'
As = RsX' + XAp'y
NT-4. Realize a latch using the pull-up, pulldown technique.
The K-map for the Y of a latch is
C
0 0 1 0
1 1 1 0 y
D Y
By inspection of this diagram, we can see that Y'+ = CD' and Y'- = CD.
This leads to the circuit below:
_Vdd
|
-
D----o|
-
|
-
C-|>o--o|
- --o<|--
| | |
-----|>o-----Q
|
-
C-----|
-
|
-
D----|
-
|
-
v (ground)
NT-5. Modify the design of the square rooter developed in class so
that, instead of a counter control, we go thru the process 4 times,
and use the action doubler to accomplish this.
Remove the While-box (and counter). Send the initiating R-signal to
the input of a doubler, the output of that doubler to a second
doubler, and the output of the second doubler to where the output of the
while-box went, i.e., to the input to the 2-step.
.............
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