Lecture Schedule for Computer Organization, CS W3824  03f
S. H. Unger

Text: Hennessy and Patterson, "Computer Organization: The
Hardware/Software Interface", Second Edition, Morgan Kaufmann, 1998

Note: This is only a PRELIMINARY, ROUGH schedule.  It will be modified
as the semester progresses.  Some topics not listed here may
be covered.

1. Course Procedures.  Basic Structure of a Computer.  Begin
   discussion of logic circuits.

2. Boolean algebra basics.   Some Boolean theorems.  Relating circuits
to Boolean expressions.

3. Truth tables, 2-stage logic, DeMorgan laws, NAND- and NOR-gates,
   Don't cares. MUX's, distributors, decoders.

4. Realizations of MUX's with standard gates and in tree
   form. Realizing decoders in matrix form.  
   ROMs and PLAs. XOR gates: identities, tree form realizations,
   application to parity checkers.

5. Latches, Edge-triggered D-FFs.  Registers: Shift registers, register
   files.

6. Sequential circuit design.  Flow tables and state diagrams.
   Implementing a counter.

7. Review of parity checks.  Signed numbers, sign magnitude, twos
   complement.

8. Binary adders.  Analysis of binary addition derivation of circuit
   for the full adder, M-gate and 3-input XOR.  Show how these are
   linked to construct ripple carry adder.

9. Construction of ALU.  Overflow detection.  Subtraction, logic
   operations, comparison.  Faster adders; carry skip.
   MIPS assembler language.  MIPS instruction fields.  Some basic
   instructions: add, sub, lw, sw.

10. Jump and branch instructions.


11. Immediate addressing.  Implementing loops.

12. Switches, procedure calls, stacks.

13. Recursive subroutines.  Caller and callee save.  Out-of-bounds
    arguments.

14. Midterm exam.

15. Handling character strings.  ASCII code.

16. Design of simple add-and-shift multiplier.  Booth algorithm
    multiplier.  Simple multiplications using add and shift
    instructions.

17. Floating point numbers and how they are represented in computers.
    Floating point addition.

18. Floating point multiplication.

    Single-cycle implementation of the MIPS computer (start).

19. Complete single-cycle implementation of the MIPS computer.

    Multicycle implementation of the MIPS computer (start).

20. Finish multicycle implementation of the MIPS computer.

    Interrupts, exceptions, traps (start).

21. Interrupts, exceptions, traps (finish).
    Pipelining, general philosophy.  Latency versus thru-put.
    Problems with pipelines (hazards: control, branching, data.)

22. Pipelines-continued.  Data hazards and forwarding.  Delayed
    branching.

23. Start memory hierarchy.  Levels of memory, tradeoffs among size,
    speed, and cost.  Caches: spatial and temporal locality.  Hits,
    hit time, misses, miss rate, miss penalty, write thru, write back.
    Associative and direct-mapped caches.

24. Finish caches: n-way associative.  Replacement policy: LRU or
    random.
    Multi-level cache.  Interleaved memory.
    Virtual memory, general concept.

25. Virtual memory continued.  Virtual and physical addresses. Page
    sizes, page tables, page faults.  Replacement policies.  Dirty
    bit.  Protection.

26. I/O.  Types of devices: disks, tapes, printers, terminals, mice,
    modems.  Characteristics of disks.

27. I/O buses.  Polling.   Interrupt-driven I/O.  DMA.

28. Error correction and detection--Hamming code.
    Professionalism and ethics.