READ: Chapter 1 (Introduction) and Appendix B.1 and B.2 (Logic Design). Note that the discussion on p. B-10 on generating the product-of-sums form of an expression is incorrect. (What they are generating are the COMPLEMENTS of product-of-sums forms.) Don't do problem B.8 below until the proper procedure is explained in class.
Also, the term "minterm" is incorrectly used on p. B-12. What is referred to there as a minterm is a product term (or p-term). A minterm is a p-term in which ALL the variables of the function appear, either complemented or uncomplemented.
READ the material on numbers (access from the class website) and do the problems, but do NOT hand in your work. Solutions will be supplied.
PROBLEMS: In text: Appendix B/(1-3, 6, 8, 10 (first 3 parts), 14).
READ: Appendix B.3.
PROBLEMS: (For problems in the text, when asked to "write a logic function", write an efficient algebraic EXPRESSION.)
B/(11 [omit part 4], 12 [omit part 2], 18).
NONTEXT HWK PROBLEMS:
NT1. Draw circuit for a 1-8 deMUX using as components, 1-2 deMUX's
NT2. For the example worked out on p. B-17, show that a better solution exists: 3 discrete 2-input gates, and that only 3 PLA product terms are necessary.
NT3. Using only AND-gates and inverters, construct a minimal circuit realizing a 3-5 decoder. Take full advantage of the don't cares generated by the assumption that the only allowed input states are those corresponding to the binary numbers ranging from 0 to 100.
OPTIONAL (Optional problems are provided to give you the opportunity to get some extra problem-solving practice if you wish. These problems will NOT be graded. Do NOT turn them in. Solutions will be supplied along with the other problem solutions.)
OPT1 : Using 2-1 MUX's as components, implement a 5-1 MUX.
READ: 4.1, 4.2
PROBLEMS:
NT1. Using 2-input XOR-gates, design a circuit to generate a parity bit for a 5-bit word. Then design a circuit whose output is 1 if an odd number of bits are corrupted in a 6-bit (including the parity bit) word generated by the previous circuit.
NT2. Is it true that, in Boolean algebra, if X + Y = X + Z, then Y = Z? Using (+) to represent the XOR operation, is it true that if X (+) Y = X (+) Z, then Y = Z? In both cases supply proofs or counter-examples.
The following notation is used below to describe state diagrams of finite state machines. Z(i) is the output for node i. NS(s,i) is the next-state if the present state is s and the input is i.NT-3. A 2-state, 1-output state-machine is defined by: Z(1) = 0, Z(2) = 1, NS(1,0) = 2, NS(1,1) = 1, NS(2,0) = 1, NS(2,1) = 2
(a) Construct the corresponding state diagram, and flow table.
(b) If machine starts in state-1, what is the sequence of outputs, starting with the initial output, if the input sequence is 00101?
(c) Encode the flow table states by setting y=0 for state-1 and y=1 for state-2. Then complete the implementation of the machine using ETDFF's and AND -OR-INVERTER logic. Show the finished logic circuit diagram
NT-4. The flow table for a 3-state, 2-input machine is shown below, along with an encoding (in terms of y1 and y2) of the states. st AB Z y1 y2 00 01 11 10 ____________________ 1| 1 2 - - 0 0 0 2| - 3 - 1 0 0 1 3| 2 - - 2 1 1 1 Using the don't cares as best you can to simplify the logic, generate logic expressions for Y1, Y2, and Z. Then draw a logic circuit diagram, including ETDFF's, showing how it all goes together.
NT-5. Convert each of the following decimal numbers into octal numbers: (a) 80 (b) 800
NT-6. Convert each of the following octal numbers into decimal numbers. (a) 712 (b) 1010
NT-7. Convert to binary form, each of the following decimal numbers: (a) 880 (b) 666
NT-8 Convert each of the following binary numbers to decimal form (numbers are broken into blocks to make them easier to read). (a) 1010 1010 1010 (b) 10 1101 0111 (c) 1 1111 1111 (d) 11 1111 1110
NT-9. Find the simplest SOP expression equivalent to: Z=AB'C+A'CD+ABCE+E'
Read: 4.3-4.5 (thru p. 240), Chapter 3 thru 3.5.
PROBLEMS.
In Text: 4/(2-5)
Non-Text:
NT1. Show how we can add to the capabilities of the ALU discussed in class and in the text a command for generating the Boolean complement of input B.
NT2. Repeat NT1, but with the new operation being to generate the absolute value of input B. Assume that we can easily generate a 1-bit control signal ABS that is 1 when the ALU control input corresponds to the absolute value command. Don't forget to consider the case where B is the negative number with the greatest absolute value.
NT3. Design a logic circuit that compares two 4-bit (including sign) numbers, a and b, in sign-magnitude form, and produces a 1-output iff (if and only if) a = b. (You must take into account the fact that 0 can be represented in two different ways.) Let the input bits be a3, a2, a1, a0, and b3, b2, b1, and b0, where a3 and b3 are the sign bits. You may use as components any of the standard logic gates we discussed, including XOR. No need to draw the circuit, just provide a reasonably economical algebraic expression.
OPTIONAL PROBLEMS. NOT REQUIRED. Do NOT hand these in. They will NOT be graded, but solutions will be supplied.
OP-1. Convert the decimal fraction 0.432 to a 5-bit binary fraction.
OP-2. Convert the binary fraction 0.01101 to a rational decimal fraction.
READ: Same as for HW #4.
PROBLEMS: IN TEXT: 3/(4, 6, 9-11)
NT PROBLEMS
NT1. Using as building blocks the 4-bit adder block and the interior module block developed in class, draw a block diagram of a 32-bit FCLA (full carry lookahead adder).
NT2. Show a pair of 32-bit numbers, A and B, that would take the maximum amount of time for an addition with a ripple-carry adder. Would this also be an example of a maximum-time addition with the FCLA of the previous problem?
OPTIONAL PROBLEM. NOT REQUIRED. TEXT: 3.1
****DO MIDTERM COURSE EVALUATION ON WEB. Go to http://oracle.seas.columbia.edu/
Read: Appendix A, finish Chapter 3.
Problems: 3/(12, 21, 23, 24)
NT-1. Check out this recursive algorithm for computing the square of a non-negative integer n.
sq(n)
if(n == 0) return 0
else return sq(n - 1) + 2*n - 1
Implement this with a MIPS program.
NT-2. Implement the function described by Z=AB'C+BC'D with a 2-stage NAND-gate circuit. Assume double-rail inputs, i.e., that each variable is available in both complemented and uncomplemented forms.
OPTIONAL: 3/22.
*****MIDTERM EXAM COMING THURSDAY, March 4 *****
Read: 4.6-4.11
Problems: Text:4/(21, 40, 50-52)
NonText problems: For NT1 and NT2, assume a conventional (non-Booth) add-and-shift multiplier for 4-bit numbers, but modify it by using ARITHMETIC right shifts.
NT1. Suppose now we check this out for two's complement (TC) arithmetic. What is the result if the multiplicand is 1011, a negative number, and the multiplier is 0101? Is this the correct product? What if 1011 is the multiplier and 0101 is the multiplicand? Is this correct?
NT2. Now modify the multiplier further by adding the condition that the leftmost bit of the multiplier is assigned a negative weight, so that, for the last step in the process, if the multiplier bit is one, the multiplicand is SUBTRACTED instead of added. Use sign extension to fill out the 8-bit register. Try this out for the two situations specified in NT1. Are the multiplier results correct?
NT3. Below is a worked out example of Booth multiplication of two 4-bit TC numbers. We assume an 8-bit MQ register. Note that we must use sign extension for each of the product terms. That is, to fill out the eight-bit register, a number with fewer than 8 bits must be extended to the left by repeating its sign bit. Start by computing the TC of the multiplicand, which you can then use for the subtractions.
0101 TC(0101) = 1011
x1011
-----
11111011
000101
11011
-----------
11100111
Now do the same thing for the following 6-bit numbers, assuming the MQ
register is 12 bits in length.
101101
x101110
-------
NT4. Show the contents of the RQ-register, step-by-step if the division algorithm (restoring) discussed in class (Fig. 4.40 in the text appears to be incorrect) is used to divide the 6-bit TC number 010110 by 101. Assume 3-bit words, so the RQ-register has 6-bits. You can short-cut the process by NOT subtracting where you see that a negative number will result, i.e., you pretend that you did subtract and then did the restoring addition. Show the sequence of RQ-register contents, with a comment such as "shift left" associated with each step.
NT5. Repeat NT4 using the non-restoring algorithm. Now show the details of adding and subtracting.
Read: 5/(1-4)
Problems: Text 4/(25-28, 31), 5/(1, 2, 10)
NT1. Show, in detail (step-by-step), how the floating point numbers
(a) A and B below are added. A = 1011 1101 1010 0000 0000 0000 0000 0000 B = 0011 1110 1100 0000 0000 0000 0000 0000HW #9. Due: 4/8/04(b) A and C below are added. A = 1011 1101 1010 0000 0000 0000 0000 0000 C = 0011 1101 0111 0000 0000 0000 0000 0000
NT2. Show, in detail (step-by-step), how the floating point numbers C and D below are multiplied. C = 0011 1101 0111 0000 0000 0000 0000 0000 D = 1100 0101 0110 0000 0000 0000 0000 0000
NT3. Assume we have a comparator circuit that operates as follows. Its inputs are two 32-bit numbers A, and B. It has 3 outputs, labeled, A>B, B>A, and A=B. It works as you would expect under the assumption that the inputs are considered to be unsigned integers. Now suppose we need to compare two 32-bit numbers in TWO'S COMPLEMENT form. Explain how we could use the given comparator to determine for, any pair of inputs, which is larger, or that they are equal. Remember that any positive number is greater than any negative number, and that if |A| > |B|, then -|B| > -|A|. It is possible to use the given comparator for the specified purpose without adding ANY additional logic elements. But, if you can't solve it this way, do the best you can using more logic.
OPTIONAL PROBLEMS: 5/(11, 12) NTO. Bearing in mind the same two points mentioned in NT-3 above, show how to use the same comparator circuit to compare two FLOATING POINT numbers. This seems to require more hardware. One solution exists in which an AND-gate and two 2-1 MUX's are used in addition to the comparator.
Read: 5/(scan 5, 6, scan 7-10) 6/(1-3)
Problems: In text: 5/(5, 15, 17, 19) 6/(1, 2)
NT1. Give two reasons for saving the address of the instruction being executed at the time an exception occurs.
Read: 6/(5, 6), p. B-26 (SRAMS) thru B-33, scan 6/(7-12)
Problems: TEXT: 6/(3, 4, 11-16)
NON-TEXT:
NT-1. In terms of the elementary operations, RR (read a row into the
column latches), WR (write the contents of the column latches into a
row), SW (select a word to output from the column latches) and WL
(write a word into the column latches from outside the memory),
specify what must be done to:
(a) read a word out of an SRAM
(b) write a word into a SRAM
(c) read a word out of a DRAM
(d) write a word into a DRAM
NT-2. For a proposed 256 Mb DRAM chip, suppose the refreshment
rate is 5000/s (i.e., each cell must be refreshed 5000 times per
second), and the refreshment time is 10 n/row (10 nanoseconds per
row). Is there a problem here?
NT-3. Show how to build a 256 MB memory (i.e., a memory
with 256M 8-bit words) using as components 256 Mb (lower case b means
bit) memory chips configured as 64 Mx4 (i.e., 64 M 4-bit words), and a
decoder. Assume the chips have enabled tri-state outputs.