The inner FPGA logic can be seen more or less as ideal. This is because :
- the clock is distributed by a special net ( which makes it reach the flip flops in the same time)
- all types of circuit delays are modeled by the Xilinx tools;
as long as the timing analysis says "OK", the circuit is guaranteed to work.

On the other hand, the I/O signals link the FPGA core with the external devices.
To achieve a good timing, we have to consider:
- the FPGA I/O delays and electrical specs
- the PCB trace delay
- the I/O timing / electrical specs. of the external device(s) we're using

VERY IMPORTANT : I/O mistakes may make the circuit not work at all,
but very likely will generate seldom errors, even 1 in 1 million.
More, such very seldom errors may appear while modifying an "innocent" part of the design,
as this can lead to a different placement & routing of the FPGA components.

Xilinx I/O cell

Start "fpga_editor" and open the system.ncd file
Select an element of type IOB from the right text window, press on the red mirror in the toolbar,
and 2click on the big red element in the main window.

You'll see that a FPGA I/O cell is not so simple.

First, you can see in the upper right that the cell can be configured in a lot of exotic modes.
LVTTL (3.3 V) is usually used. To minimise power consumption and switching noise,
a cell can be configured as fast / slow (we'll use fast).
The strength of the output drives can also be set (usually 12mA).
There are big tables describing how to compute the delays of various cell types,
and how to make corrections due the external capacitive load.

A lot of devices are connected to the XSB general bus.
Using F12 drives (fast, 12mA) --- the default --- I got very seldom errors on data bits 3 and 5.
That's why in "pad_io.vhd" the bus drives are instanciated to F24.

You can also see that there are 3 flip-flops inside a I/O cell
(1 for input, and 2 for output --- the 2nd for the 3state operation).
They work identically with a regular flip-flop, but they are very "close" to the I/O cell.

These I/O bounded flip-flops can be used or not.
It is a GOOD practice to use them in most cases because the path from the I/O pad to such f-f
is very short, and it does not contain complicated internal "wires". Advantages:
- the circuit can operate at "higher" frequency ( read : otherwise it can be too slow)
- the I/O signals will be synchroninous to each other

I noticed extremelly small glitches on my 16 bit truecolor framebuffer.
I thought it is the effect of staring to the monitor for too many hours.
When I changed it to 8 bit (the version you have) I noticed that the glitches were very real.
I had forgotten to "pack" the video out flip-flops to the I/O pads !
(in pad_io.vhd and svga.vdh you can see the strange iob attribute)


You may wonder how the internal / external clocks are synchronised to each other.
You don't need it for the labs, but it is not trivial at all and requires in-depth knowledge of
 the circuit you're using.

Briefly, there are special elements in the FPGA which can synchronize the internal clocks,
and can compensate the I/O delays to keep synchronization with the external ones.

Our master clock (the same microblaze is using) runs at 50MHz.
The VGA pixel clock runs at 25Mhz.
They are both internal clocks.
The two clocks are synch., so it is much simpler to design the elements between the 2 clock domains.

Slow devices (s.a. a serial audio codec or the PS/2 keybd/mouse) use the data on the negedge of
the clock. This trick works as the circuit delays are much smaller than the clock period, so no
fancy synch. is required.
One the other hand, fast devices (such as DDR or multigigabit transceivers) require exquisite