Steven M. Nowick is a Professor of Computer Science and Electrical Engineering at Columbia University. He was also Chair of the Computer Engineering Program (2008-2013), which he co-founded in 1994. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University. His main research area is on design methodologies and CAD tools for synthesis and optimization of asynchronous and mixed-timing (i.e. interfacing multiple clocked and/or asynchronous domains) digital systems. His current projects include: scalable networks-on-chip (NoC's) for shared-memory parallel processors and embedded systems, ultra-low-energy digital systems, low-power and robust global communication, computer-aided design, and fault tolerance.
Dr. Nowick is an IEEE Fellow (2009). He received an Alfred P. Sloan Research Fellowship (1995, one of 10 awardees in all areas of computer science), an NSF CAREER Award (1995), and an NSF Research Initiation Award (RIA) (1993). He also received several Best Paper Awards: IEEE International Conference on Computer Design (both in 1991 and 2012) and the IEEE Async Symposium (2000).
He is co-founder of the IEEE "Async" Symposia series, and served as Program Committee Co-Chair and General Co-Chair. He was also Program Chair of the IEEE/ACM International Workshop on Logic and Synthesis. He served as Sub-Committee or Track Chair for the program committees of several leading design and CAD conferences: ACM/IEEE Design Automation Conference (DAC) (logic/high-level synthesis/FPGA's), ACM/IEEE Design, Automation and Test in Europe (DATE) Conference (logic/technology-dependent synthesis), and IEEE International Conference in Computer Design (ICCD) (tools and methodologies). He is currently associate editor of ACM Journal on Emerging Technologies in Computer Systems, and was former associate editor of IEEE Transactions on Computer-Aided Design and IEEE Transactions on VLSI Systems. He has been a member of many leading program committees, including DAC, ICCAD, DATE, NOCS, Async, VLSI Design, ICCD and IWLS.
His recent research has been funded by NSF awards, including for continuous-time DSP's (2010) and low-latency asynchronous interconnection networks (2012, 2008), among others. In 2000, he received two medium-scale NSF ITR awards for asynchronous research. He was brought onto the DARPA "CLASS" project (2005), headed by Boeing, to create a new commercially-viable CAD tool flow for designing asynchronous systems.
Dr. Nowick was the selection committee chair of the ACM/SIGDA
"Outstanding PhD Dissertation in Electronic Design Automation" award (2012-2013),
and served as a member of the ACM/IEEE DAC Best Paper Award committee (2010).
He is also a recipient of the Columbia Engineering School "Distinguished
Faculty Teaching Award" (2011). He holds 11 issued US patents.