PUBLICATIONS:

JOURNAL ARTICLES:

•  "A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors,"

M. Benes, S.M. Nowick and A. Wolfe.  To appear in IEEE Transactions on VLSI Systems (2001).
 
• ``Synthesis for Logical Initializability of Synchronous Finite  State Machines,''

M. Singh and S.M. Nowick.   IEEE Transactions on VLSI Systems, vol. 8:5, pp. 542-557 (October 2000).
 
• ``Modeling and Design of Asynchronous Circuits'' (Invited Paper),

M.B. Josephs, S.M. Nowick and C.H. van Berkel, Proceedings of the IEEE, vol. 87:2,
pp. 234-242 (February 1999).
 
• ``Scanning the Technology:  Applications of Asynchronous Circuits'' (Invited Paper),

C.H. van Berkel, M.B. Josephs and S.M. Nowick, Proceedings of the IEEE, vol. 87:2,
pp. 223-233 (February 1999).
 
• ``Fast Heuristic and Exact Algorithms for Two-Level Hazard-Free Logic Minimization,''

M. Theobald and S.M. Nowick, IEEE Transactions on Computer-Aided Design, vol. 17:11,
pp. 1130-1147 (November 1998).
 
• ``Architectural Optimization for Low-Power Non-Pipelined Asynchronous Systems,''

L.A. Plana and S.M. Nowick, IEEE Transactions on VLSI Systems, vol. 6:1,
pp. 56-64 (March 1998).
 
• ``Synthesis of Asynchronous Circuits for Stuck-at and Robust Path Delay Fault Testability,''

S.M. Nowick, N.K. Jha and Fu-Chiung Cheng, IEEE Transactions on Computer-Aided Design,
vol. 16:12, pp. 1514-1521 (December 1997).
 
• ``Design of a Low-Latency Asynchronous Adder Using Speculative Completion,''

S.M. Nowick,  IEE Proceedings - Computers and Digital Techniques, vol. 143, no. 5,
pp. 301-307 (September 1996).
 
• ``Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input  Changes,''

S.M. Nowick and D.L. Dill,  IEEE Transactions on Computer-Aided Design, vol. 14:8,
pp. 986-997 (August 1995).
 
• ``A Correctness Criterion for Asynchronous Circuit Validation and Optimization,''

G. Gopalakrishnan, E. Brunvand, N. Michell and S.M. Nowick, IEEE Transactions on
Computer-Aided Design, vol. 13:11, pp. 1309-1318 (November 1994).
 
• ``The Design of a High-Performance Cache Controller: a Case Study in Asynchronous Synthesis,''

S.M. Nowick, M.E. Dean, D.L. Dill and M. Horowitz, Integration:  the VLSI Journal,
vol. 15:3, pp. 241-262 (October 1993).
 
• ``Specification and Automatic Verification of Self-Timed Queues,''

D.L. Dill, S.M. Nowick and R.F. Sproull,  Formal Methods in System Design, vol. 1:1,
pp. 29-60 (July 1992).

REFEREED CONFERENCE PAPERS:

• "MOUSETRAP:  Ultra-High-Speed Transition-Signaling Asynchronous Pipelines,"

M. Singh and S.M. Nowick.  IEEE International Conference on Computer Design (ICCD),
Austin, TX (September 2001).
 
• "Transformations for the Synthesis and Optimization of Asynchronous Distributed Control,"

M. Theobald and S.M. Nowick.  IEEE/ACM Design Automation Conference (DAC),
Las Vegas, NV (June 2001).
 
• "Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols,"

T. Chelcea and S.M. Nowick.  IEEE/ACM Design Automation Conference (DAC),
Las Vegas, NV (June 2001).
 
• "Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications,"

M. Singh and S.M. Nowick.  IEEE Computer Society Annual Workshop on VLSI (WVLSI),
Orlando, FL (April 2000).
 
• "A Low-Latency FIFO for Mixed-Clock Systems,"

T. Chelcea and S.M. Nowick.  IEEE Computer Society Annual Workshop on VLSI (WVLSI),
Orlando, FL (April 2000).
 
• "High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths,"

M. Singh and S.M. Nowick.   Best Paper Award,  IEEE "Async-00" Symposium (6th IEEE
Int. Symp. on Advanced Research in Asynchronous Circuits and Systems), Eilat, Israel (April 2000).
 
• "Low-Latency Asynchronous FIFO's Using Token Rings,"

T. Chelcea and S.M. Nowick.   IEEE "Async-00" Symposium (6th IEEE
Int. Symp. on Advanced Research in Asynchronous Circuits and Systems), Eilat, Israel (April 2000).

• "OPTIMISTA :  State Minimization of Asynchronous FSMs for Optimum Output Logic,"

R.M. Fuhrer and S.M. Nowick.  IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), San Jose, CA (1999).
 
• ``A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors,`'

M. Benes, S.M. Nowick and A. Wolfe.  IEEE Async-98 Symposium (4th IEEE Int. Symp. on
Advanced Research in Asynchronous Circuits and Systems), San Diego, CA (1998).
 
• ``An Implicit Method for Hazard-Free Two-Level Logic Minimization,''

M. Theobald and S.M. Nowick. Best Paper Finalist, IEEE Async-98 Symposium
(4th IEEE Int. Symp. on Advanced Research in Asynchronous Circuits and Systems),
San Diego, CA (1998).
 
• ``OPTIMIST: State Minimization for Optimal 2-Level Logic Implementation,''

R.M. Fuhrer and S.M. Nowick.  IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), San Jose, CA (1997).
 
• ``A High-Speed Asynchronous Decompression Circuit for Embedded Processors,''

M. Benes, A. Wolfe and S.M. Nowick.  17th Conference on Advanced Research in VLSI,
Ann Arbor, Michigan (1997).
 
• ``Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders,''

S.M. Nowick, K.Y. Yun, P.A. Beerel and A.E. Dooply.   IEEE Async-97 Symposium
(3rd IEEE Int. Symp. on Advanced Research in Asynchronous Circuits and Systems),
Eindhoven, Netherlands (1997).
 
• ``Synthesis of Low-Power Asynchronous Circuits in a Specified Environment,''

S.M. Nowick and M. Theobald.  IEEE International Symposium on Low Power Electronics and Design,
Monterey, CA (1997).
 
• ``Synthesis for Logical Initializability of Synchronous Finite State Machines,''

M. Singh and S.M. Nowick.  10th International Conference on VLSI Design, Hyderabad, India (1997).
 
• ``Synthesis-for-Initializability of Asynchronous Sequential Machines,''

M. Singh and S.M. Nowick.  IEEE International Test Conference, Washington, DC (1996).
 
• ``Concurrency-Oriented Optimization for Low-Power Asynchronous Systems,''

L.A. Plana and S.M. Nowick.  IEEE International Symposium on Low Power Electronics and Design,
Monterey, CA (1996).
 
• ``Espresso-HF:  A Heuristic Hazard-Free Minimizer for Two-Level Logic,''

S.M. Nowick, M. Theobald and T. Wu.  33rd IEEE/ACM Design Automation Conference (DAC),
Las Vegas, NV (1996).
 
• ``Synthesis of Hazard-Free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes,''

P. Kudva, G. Gopalakrishnan, H. Jacobson and S.M. Nowick.  33rd IEEE/ACM Design Automation Conference
(DAC), Las Vegas, NV (1996).
 
• ``Estimation and Bounding of Energy Consumption in Burst-Mode Control Circuits,''

P.A. Beerel, K.Y. Yun, S.M. Nowick and P. Yeh.  IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), San Jose, CA (1995).

• ``Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines,''

R.M. Fuhrer, B. Lin and S.M. Nowick.  IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), San Jose, CA (1995).

• ``Algorithms for the Optimal State Assignment of Asynchronous State Machines,''

R.M. Fuhrer, B. Lin and S.M. Nowick.  16th Conference on Advanced Research in VLSI,
Chapel Hill, NC (1995).

• ``Synthesis of Asynchronous Circuits for Stuck-at and Robust Path Delay Fault Testability,''

S.M. Nowick, N.K. Jha and F.-C. Cheng. 8th International Conference on VLSI Design,
New Delhi, India (1995).

• ``UCLOCK:  Automated Design of High-Performance Unclocked State Machines,`'

S.M. Nowick and B. Coates.  IEEE International Conference on Computer Design (ICCD),
Cambridge, MA (1994).

• ``Practical Generalizations of Asynchronous State Machines,''

K.Y. Yun, D.L. Dill and S.M. Nowick.  European Conference on Design Automation (EDAC),
Paris, France (1993).

• ``The Design of a High-Performance Cache Controller: a Case Study in Asynchronous Synthesis,''

S.M. Nowick, M.E. Dean, D.L. Dill and M. Horowitz.  Best Paper Award, Asynchronous Circuits and
Systems Minitrack/Best Paper Finalist, Architecture Track, 26th IEEE Hawaii International Conference
on System Sciences (HICSS), Maui, HI (1993).

• ``Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes,''

S.M. Nowick and D.L. Dill.  IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), Santa Clara, CA (1992).

• ``Practical Asynchronous Controller Design,''

S.M. Nowick, K.Y. Yun and D.L. Dill.  IEEE International Conference on Computer Design
(ICCD), Cambridge, MA (1992).

• ``Synthesis of 3D Asynchronous State Machines,''

K.Y. Yun, D.L. Dill and S.M. Nowick.  IEEE International Conference on Computer Design
(ICCD), Cambridge, MA (1992).

• ``Automatic Synthesis of Locally-Clocked Asynchronous State Machines,''

S.M. Nowick and D.L. Dill.  IEEE International Conference on Computer-Aided Design
(ICCAD), Santa Clara, CA (1991).

• ``Synthesis of Asynchronous State Machines Using a Local Clock,''

S.M. Nowick and D.L. Dill. Best Paper Award, CAD track,
IEEE International Conference on Computer Design (ICCD), Cambridge, MA (1991).

• ``Practicality of State-Machine Verification of Speed-Independent Circuits,''

S.M. Nowick and D.L. Dill.  IEEE International Conference on Computer-Aided Design
(ICCAD), Santa Clara, CA (1989).
 
• ``Automatic Verification of Speed-Independent Circuits with Petri Net Specifications,''

D.L. Dill, S.M. Nowick and R.F. Sproull. IEEE International Conference on Computer Design
(ICCD), Cambridge, MA (1989).

INVITED CONFERENCE PAPERS:

• ``Practical Advances in Asynchronous Design and Asynchronous/Synchronous Interfaces,''

E. Brunvand, S.M. Nowick and K.Y. Yun, 36th ACM/IEEE Design Automation Conference (DAC),
New Orleans, LA (1999).
 
• ``Practical Advances in Asynchronous Design,''

E. Brunvand, S.M. Nowick and K.Y. Yun.  IEEE International Conference on Computer Design
(ICCD), Austin, Texas (1997).

REFEREED WORKSHOP PAPERS:

• "MOUSETRAP:  Ultra-High-Speed Transition-Signaling Asynchronous Pipelines,"

M. Singh and S.M. Nowick.  Presented at  ACM TAU-00 Workshop
(Eighth ACM/SIGDA Workshop on TIming Issues in the Specification and Synthesis
of Digital Systems), Austin, TX (2000).
 
• ``Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces,''

E. Brunvand, S.M. Nowick and K.Y. Yun.  Invited survey article (not refereed).  ACM TAU-99 Workshop
(Seventh ACM/SIGDA International Workshop on Timing Issues in the Specification and Synthesis
of Digital Systems), Monterey, CA (1999).
 
• ``MINIMALIST:  An Environment for the Synthesis and Verification of Burst-Mode Asynchronous Machines,''

R.M. Fuhrer, S.M. Nowick, M. Theobald, N.K. Jha, and L. Plana. Poster presentation at IEEE International
Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA (1998).
 
• ``Exact Optimal State Minimization for 2-Level Output Logic,''

R.M. Fuhrer and S.M. Nowick. Presented at IEEE International Workshop on Logic Synthesis
(IWLS),  Lake Tahoe, CA (1998).
 
• ``State Assignment for Initializability of Synchronous Finite State Machines,''

M. Singh and S.M. Nowick.  Presented at IEEE International Test Synthesis Workshop
(ITSW), Santa Barbara, CA (1996).
 
• ``Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines,''

R.M. Fuhrer, B. Lin and S.M. Nowick. Presented at IEEE International Workshop on Logic Synthesis
(IWLS), Lake Tahoe, CA (1995).
 
• ``Automated Design of High-Performance Unclocked State Machines,''

S.M. Nowick and B. Coates.  Presented at TAU-93 Workshop (ACM/SIGDA Workshop on
Timing Issues in the Specification and Synthesis of Digital Systems), Malente, Germany (1993).
 
• ``Asynchronous State Machine Synthesis Using a Local Clock,''

S.M. Nowick and D.L. Dill.  Presented at IEEE International Workshop on Logic Synthesis
(IWLS), Research Triangle Park, NC (1991).

BOOKS:

"Sequential Optimization of Asynchronous and Synchronous Finite-State Machines:  Algorithms and Tools."
R.M. Fuhrer and S.M. Nowick.  Kluwer Academic Publishers (Boston, MA), 2001.  ISBN 0-7923-7425-8.

BOOK CONTRIBUTIONS:

• ``An Introduction to Asynchronous Circuit Design,''

A. Davis and S.M. Nowick.  Article in The Encyclopedia of Computer Science and Technology,
vol. 38 (A. Kent and J.G. Williams, eds.), Marcel Dekker, New York (February 1998).
 
• ``Asynchronous Circuit Design:  Motivation, Background and Methods,''

A.L. Davis and S.M. Nowick.  Chapter in Asynchronous Digital Circuit Design,
G. Birtwistle and A. Davis editors, Springer-Verlag (Workshops in Computing Series, 1995),
pp. 1-49.
 
• ``Specification and Automatic Verification of Self-Timed Queues,''

D.L. Dill, S.M. Nowick and R.F. Sproull. Chapter in Formal Verification of Hardware Design
(IEEE Tutorial Series), M. Yoeli editor (Computer Science Press of IEEE, 1991).
(Originally appeared as Stanford University Technical Report, Computer Systems Laboratory,
CSL-TR-89-387, August 1989.)
 
• ``Automatic Verification,''

S.M. Nowick and D.L. Dill. Chapter in T. H.-Y. Meng, Synchronization Design for Digital Systems,
Kluwer Academic (1990).