I am a Professor of Computer Science and Electrical Engineering at Columbia University, and also chair of the Computer Engineering Program.  I received my Ph.D. in Computer Science from Stanford University in 1993, and B.A. from Yale University.  My Ph.D. dissertation introduced an automatic synthesis method for "locally-clocked" asynchronous state machines, and I formalized the asynchronous controller specification style called "burst-mode".  My current research areas include:  asynchronous circuits, VLSI CAD, low-power and high-performance digital design, logic synthesis, and formal verification of finite-state concurrent systems.

Professional Activities and Awards

I received an NSF Faculty Early Career (CAREER) Award (1995), an Alfred P. Sloan Research Fellowship (1995) (one of only ten awardees nationally in computer science that year) and an NSF Research Initiation Award (RIA) (1993).  I  received  Best Paper Awards at the IEEE Async Symposium (2000) and the IEEE International Conference on Computer Design (1991), and was Best Paper Finalist at  the  IEEE Async Symposium (in 2008 [2 papers], 2003, 2002 and 1998) and at the  Hawaii International Conference on System Sciences (HICSS 1993). I am also an IEEE Fellow (2009).

I co-founded the IEEE  "Async" Symposia series in 1994 (with colleagues Erik Brunvand, Al Davis and Ganesh Gopalakrishnan of University of Utah) (officially called the "IEEE International Symposium on Asynchronous Circuits and Systems"). I was also its Program Co-Chair twice (1994, 1999) and General Co-Chair once (2005). I was also Program Committee Chair of IWLS-02 (11th IEEE/ACM Int. Workshop on Logic and Synthesis) , Program Track Chair for the "Tools and Methodology Track" of the IEEE International Conference on Computer Design (2005), and Topic Area Chair and Co-Chair for the "Logic and Technology-Dependent Synthesis for Deep-Submicron Circuits" area of the IEEE Design, Automation and Test in Europe (DATE) Conference (2009, 2008, respectively). I have also been a Program Committee Member for a number of leading  international conferences and workshops:  DAC (IEEE/ACM Design Automation Conference), ICCAD (IEEE/ACM International Conference on Computer -Aided Design), DATE (Design Automation and Test in Europe), ICCD (IEEE International Conference on Computer Design),  IWLS (IEEE International Workshop on Logic Synthesis),  ARVLSI (Conference on Advanced Research in VLSI), Async (IEEE International Symposium on Asynchronous Circuits and Systems), TAU (ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems), VLSI Design (India), GLVLSI (Great Lakes VLSI Symposium), and the Israel Workshop on Asynchronous Circuits and Systems. I also have 8 issued U.S. patents.

I am currently an Associate Editor of IEEE Transactions on Computer-Aided Design,  and was until recently associate editor of IEEE Transactions on VLSI Systems.  I was also a Guest Editor of a special issue of Proceedings of the IEEE, vol.  87:2  (Feb. 1999) on asynchronous circuits and systems.  This issue is a good overview of recent advances in asynchronous design.  It includes 2 introductory articles and  10 research articles.  Several of the articles describe fabricated asynchronous chips (embedded and parallel processors, power-down circuitry, FIR filters, high-speed FIFO's) which exhibit quantitative advantages over comparable synchronous designs in terms of power, performance or electromagnetic compatibility.

CAD Tools

My CAD (computer-aided design) tools for asynchronous digital design are part of the CaSCADE tool environment. This environment includes three packages from my group (and three packages from USC), all available for free download and use, all accompanied by detailed tutorials, setup instructions, benchmarks, and worked-out examples: MINIMALIST , a package for synthesis and optimization of asynchronous "burst-mode" controllers; ATN-OPT , a package for synthesis of robust low-power circuits; and DES-Analyzer , for performance analysis of concurrent systems. The tools are designed for Linux platforms. To download the tools, or just to look over the tutorial slides, click here. For a writeup on our tool release in EE Times (Europe), click here.

Grants and Technology Transfer

I recently received a large-scale NSF team award (total of nearly $1 million) for "Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability Through Asynchrony" (co-PI:  Prof. Uzi Vishkin, University of Maryland). This award was one of only two large-scale "team" proposals awarded by NSF in the "Design Automation for Micro and Nano Systems" topical area for this CPA solicitation. The goal of this proposal is to develop a first-of-its-kind partly-asynchronous/partly-synchronous high-end massively-parallel-on chip computer. In particular, a high-speed, low-power asynchronous communication fabric will be developed, to connect synchronous processors, and which is robust and flexible in the presence of timing variability and multiple clock rates and supports a 'plug-and-play' assembly of low-power complex parallel processors. For the story on the SEAS web site (Summer 2008), click here.

I have also collaborated with NASA Goddard Space Center (Greenbelt, MD) (2006-2008) in designing a low-power high-speed prototype asynchronous chip for space measurement . I co-designed the chip with NASA engineers, which used my burst-mode controller design style and my Minimalist CAD package. The chip shows promise for future applications in space missions.

In 2005, I was invited to join the DARPA "CLASS" Project (2005-2007). This is the largest US government research program for asynchronous digital design in the last 30 years, with total funding of $14 million. Its goal is to make asynchronous digital design viable for the commercial and military sectors. There were approximately 20 large-scale proposals submitted, and only 1 contract funded, headed by Boeing (as PI), with participation of Philips Semiconductors (via its incubated asynchronous startup, called Handshake Solutions), two other asynchronous startups and two smaller academic efforts. The two goals of the project are: (i) building a large-scale asynchronous demonstration chip (for Boeing military applications), and compare its performance and cost to an equivalent synchronous chip; and (ii) provide a ``legacy asynchronous CAD tool'' for future asynchronous designs. I was brought onto the project for its Phase 2/3, along with my former PhD student Montek Singh (currently an assistant professor at UNC), to play a key role in (a) developing CAD tools for designing asynchronous circuits for the project, and (b) transferring my high-speed patented asynchronous circuit technology, i.e. ``Mousetrap'' pipelines, into these tools. As part of this project, we developed CAD tools for systematically optimizing very robust asynchronous circuits (currently designed through the unoptimized commercial flow at Theseus Logic, Inc.), as well as transferring our Mousetrap pipelines to Handshake Solutions for experimental incorporation as a "high-speed option" in their commercial asynchronous tool flow.

I also received two medium-scale NSF ITR awards (total of $2.5 million) in 2000 for research on asynchronous design.  One award, "A CAD Framework for the Design and Optimization of Large-Scale Asynchronous Digital Systems" (co-PI:  Prof. Peter Beerel, USC), is to develop a comprehensive and practical CAD tool for designing and optimizing large asynchronous systems.    The second award, "Asynchronous Digital Signal Processing for the Software Radio" (PI:  Prof. Ken Shepard, Columbia EE Dept.), is to apply asynchronous techniques to the design of  3rd generation wireless systems. The ITR awards are supported under special Congressional funding for "long-term risk-taking research" in information technology.  Only 62 medium- and large-scale awards were granted out of 920 submitted proposals nationally in the year 2000, across all areas of information technology. I was one of only 4 researchers nationally to receive two such medium-scale ITR awards in that year.  For the cover story in Columbia Engineering News (Fall 2000), click here.
 

For a DETAILED CV,  click here.