IWLS 2000 Program

Tuesday May 30

18.00 - 19.00 Cocktail hour

Wednesday May 31

7.15 - 8.00 Breakfast

8.00 - 9.15 Session 1: Flexibility in Logic

Moderator: Hamid Savoy

1. Don't Care Wires in Logical/Physical Design
   Philip Chong, Yunjian Jiang, Sunil Khatri, Fan Mo, Subarna Sinha, Robert Brayton
2. Synthesis by Language Equation Solving
   Nina Yevtushenko, Tiziano Villa, Robert Brayton, Alex Petrenko, Alberto Sangiovanni-Vincentelli
3. Don't Cares and Multi-Valued Logic Minimization
   Yunjian Jiang, Robert K. Brayton

9.15 - 10.00 Coffee and poster session 1: BDDs

1. Analysis of Composition Complexity, and How to Obtain Smaller Canonical Graphs.
   Jawahar Jain, Kartik Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu
2. BDD Variable Ordering Using Window-based Sampling
   Yuan Lu, Jawahar Jain, Koichiro Takayama
3. Identifying Stuck-at Faults with Vertex Precedent BDDs
   Andre Reis, Alex Prado, Marcelo Lubaszewski
4. Adjusting a Genetic Methodology for the ROBDD Optimization
   Juan A. Gómez Pulido, Juan M. Sánchez Pérez, Andrés Caro Lindo, Gabriel Ocaña Fuertes, Miguel A. Vega Rodríguez
5. Optimizing Partitioning of Transition Relations by Using High-Level Information
   Christian Stangier, Ulrich Holtmann, Christoph Meinel
6. The FLaSH Project: Resource-Aware Synthesis of Declarative Specifications
   Alan Mycroft, Richard Sharp

10.00 - 11.15 Session 2: Factorization and Decomposition

Moderator: Diana Marculescu

1. Semi-Algebraic Methods for Multi-Valued Logic
   Minxi Gao, Robert K. Brayton
2. Structure-Aware Functional Decomposition in Logic Synthesis
   Victor N. Kravets, Karem A. Sakallah
3. Logic Circuits Based on or-Binary Decision Diagrams
   Reginaldo Tavares, Michel Berkelaar

11.15 - 12.15 Focus groups

12.15 - 13.30 Lunch

13.30 - 14.45 Session 3: Technology Mapping and FPGAs

Moderator: Masahiro Fujita

1. ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
   Wolfgang Guenther, Rolf Drechsler
2. A New Expansion of Symmetric Functions and Their Application to Non-Disjoint Functional Decompositions for LUT Type FPGAs
   Tsutomu Sasao
3. A Layout-driven Logic Decomposition Model
   Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya

14.45 - 15.30 Coffee and poster session 2: Boolean reasoning

1. An Experimental Evaluation of Conflict Diagnosis and Recursive Learning in Boolean Satisfiability
   Fadi A. Aloul, Karem A. Sakallah
2. Permutation Independent Comparision of Pseudo Boolean Functions
   Riccardo Forth, Paul Molitor
3. Efficient Verification of the PCI Local Bus using Boolean Satisfiability
   Fadi A. Aloul, Karem A. Sakallah
4. Block Compatibility Approach for Column Minimization Problem in Functional Decomposition
   Muthukumar Venkatesan, Robert Bignall, Henry Selvaraj
5. A Sufficient Condition for Detecting AND-OR-AND-Type Logic
   Elena Dubrova, Mikael Millberg, Andrew J. Sullivan

15.30 - 16.45 Session 4: BDDs - I

Moderator: Shin-Ichi Minato

1. Streaming BDD Manipulation Algorithm
   Shin-ichi Minato
2. Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation
   Wolfgang Guenther, Rolf Drechsler, Stefan Hoereth
3. Minimization of Free BDDs using Evolutionary Techniques
   Wolfgang Guenther

16.45 - 18.00 panel

19.00 Dinner

Thursday June 1

7.15 - 8.00 Breakfast

8.00 - 9.15 Session 5: SAT and Equivalence Checking

Moderator: Steven Nowick

1. On-the-Fly Compression of Logical Circuits
   Malay K. Ganai, Andreas Kuehlmann
2. Improving SAT: Stack-Based Incremental Satisfiability
   Joonyoung Kim, Jesse Whittemore, Karem Sakallah
3. Using SAT in Combinational Equivalence Checking
   Evgueni I. Goldberg, Mukul R. Prasad, Robert K. Brayton

9.15 - 10.00 Coffee and poster session 3: Power

1. Accurate Power Estimation Using Circuit Partitioning
   Ana T. Freitas, Arlindo L. Oliveira, Horacio C. Neto
2. Accurate Modeling of Capacitance and Power in Logic Level Circuits
   João Baptista Martins, Ricardo Reis, José Monteiro
3. Reducing Power Consumption by Using CMOS Complex Gates
   Andre Reis
4. Complexity Issues in Gate Duplication
   Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh

10.00 - 11.15 Session 6: Power

Moderator: Soha Hassoun

1. Low Power Optimization Technique for BDD Mapped Circuits
   Per Lindgren, Mikael Kerttu, Mitch Thornton
2. Minimizing Leakage Power in CMOS Circuits Operating in Stand-By Mode
   Srinath R. Naidu, Michel Berkelaar
3. On The Complexity Of Power Estimation Problems
   Ana T. Freitas, Horacio C. Neto, Arlindo L. Oliveira

11.15 - 12.15 Focus groups

12.15 - 13.30 Lunch

13.30 - 14.45 Session 7: Novel Circuits

Moderator: Luciano Lavagno

1. Transformations for the Synthesis of Asynchronous Distributed Control
   Michael Theobald, Steven M.Nowick
2. Synthesis and Simulation of Phased Logic Systems
   Robert B. Reese, Cherrice Traver
3. A Comparison of Logical Efficiency of Reversible and Conventional Gates
   Pawel Kerntopf

14.45 - 15.30 Coffee and poster session 4: Logic

1. Layout-driven Logic Optimization
   Robert Carragher, Rajeev Murgai, Supratik Chakraborty, Mukul R. Prasad, Ankur Srivastava, Navin Vemuri
2. Logic Synthesis of a 100MHz Quadrature Decoder using Natural Logic, a Cool Runner CPLD and Free EDA Software
   Charles Moeller
3. Using Reconfigurable Hardware to Automated Visual Inspection of Commercial Ham Samples
   Miguel Ángel Vega Rodríguez, Juan Manuel Sánchez Pérez, Juan Antonio Gómez Pulido
4. Multi-Level Logic Optimization Using Node Complementation
   Kenshu Seto, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada
5. Improving the Accuracy of Statistical Delay Calculation
   Etienne Jacobs, Michel Berkelaar

15.30 - 16.45 Session 8: Layout

Moderator: Michel Berkelaar

1. Regularity Driven Logic Synthesis
   Thomas Kutzschebauch, Leon Stok
2. Layout-driven Area Constrained Timing Optimization by Net Buffering
   Rajeev Murgai
3. A Stochastic Model for Interconnection Complexity based on Rent's Rule
   Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout

18.00 Banquet at the Aegean Cafe, Laguna Beach

Friday June 2

7.45 - 8.30 Breakfast

8.30 - 9.20 Session 9: Delay

Moderator: Leon Stok

1. An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays
   Arlindo Oliveira, Rajeev Murgai
2. Sources and Quantification of Delay Variations in a 250nm CMOS Digital Cell Library
   Michel Berkelaar, Etienne Jacobs, Josep Maria Puig

9.20 - 10.10 Session 10: BDDs - II

Moderator: Robert Brayton

1. Representation of Multiple-Valued Functions with Mod-p Decision Diagrams
   Harald Sack, Elena Dubrova, Christoph Meinel
2. WWW.BDD-PORTAL.ORG
   Christoph Meinel, Arno Wagner

10.10 - 10.30 Coffee break

10.30 - 12.00 Focus groups presentations and discussion

12.00 Lunch and public next IWLS planning meeting