============================================================================= **COURSE ANNOUNCEMENT: FALL-15** *CSEE 4823x ADVANCED LOGIC DESIGN *(CSEE designates a joint course between computer science and electrical engineering) Instructor: Prof. Steven Nowick office: 508 CS Building email: nowick@cs.columbia.edu Time: Tuesday/Thursday 2:40-3:55 pm Room: to be announced ============================================================================= COURSE DESCRIPTION: This is an advanced course on modern digital design. It provides a strong foundation for computer engineering, computer science and electrical engineering courses in digital and embedded systems, computer architecture, parallel systems, networking, etc., and a good background for a variety of industry positions. Its focus is on advanced topics, with a special focus on RTL (register-transfer level) design -- top-down design of entire complex digital systems from initial specification through implementation. It also covers practical aspects of modern commercial design, including use of hardware description languages (e.g. VHDL) for modelling and simulating systems, low power optimization strategies, fault tolerance (error detection/correction), advanced adder/multiplier design, testing and testability, synchronization across clock domains, and asynchronous design. It is suitable as an elective for BS/MS/PhD degrees in computer science and electrical engineering, and for the BS/MS in computer engineering (it is one of two alternative required courses for computer engineering BS students). The course will include 2 projects: (i) complete design and simulation of an industrial controller, following commercial specifications (such as for NXP/Philips' I2C serial bus), modelling with VHDL and using Altera Quartus simulation package; (ii) complete RTL design of an entire custom digital system, from top-level specification to detailed implementation, exploring performance optimization techniques. Recent examples include: - a trigonometric hardware accelerator, - floating-point add/multiply unit, - on-chip network router with error handling. DETAILED TOPICS: Introduction to modern system-level design: Register-transfer level (RTL), algorithmic state machine models (ASMs), datapath/control allocation and interconnection. System-level performance optimization: resource sharing, scheduling, inner loop optimization, parallel vs. serial organization, area/delay/power tradeoffs. Introduction to VHDL (an industry-standard hardware description language): Hands-on modelling and simulation of digital systems using Altera CAD tools. Structural, dataflow and behavioral models. Specifying combinational and sequential blocks. Synthesis-oriented coding styles. Large-scale digital system case studies: Designing and optimizing a custom floating point unit; counting and pattern detection units; the Philips/NXP I2C commercial serial bus interface; fault-tolerant on-chip router nodes; encryption/decryption units. Designing and optimizing digital controllers: Mealy and Moore finite state machines (FSM's) design, optimal state encoding and state partitioning. Iterative circuits. Advanced high-performance adders: Conditional sum, carry-skip, carry-select, carry-lookahead, parallel prefix tree adders (Kogge-Stone, Brent-Kung). Higher-radix arithmetic. Power/area/latency tradeoffs. Combinational array multipliers: Using carry-save addition for optimization. Modern low-power design techniques: Clock gating for controller optimization; pre-computation logic for pipelined sequential systems; low-power bus encoding techniques. Introduction to fault-tolerance and error detection/correction: Hamming and parity codes, 2-dimensional (i.e. product) codes, cyclic redundancy codes (CRC) for Ethernet, etc. Recent work on mitigating soft (transient) errors due to cosmic rays. Introduction to testability and design-for-test (DfT): Fault models, built-in self-test (BIST) techniques, scan structures, test pattern generation. Asynchronous (i.e. clockless) digital circuits: Controller design, high-speed pipelines. Hazard-free logic synthesis. Metastability and synchronizers. Miscellaneous topics: Introduction to FPGA's: Xilinx internals and micro-architecture. Pseudo-random number generators (LFSR's). Floating-point arithmetic. HOMEWORKS, LAB COMPONENT AND PROJECT: The course will include a number of written homeworks, small lab design exercises, as well as a substantial medium-sized design project. You will develop good familiarity with modelling circuits and systems in VHDL, and simulating them in an Altera CAD environment. However, this is not primarily a project class. PRE-REQUISITES: basics of digital logic, such as CSEE 3827 Fundamentals of Computer Systems or the equivalent introductory course on digital design. In particular, it is assumed that you are already familiar with: Boolean algebra; combinational logic design (Karnaugh maps, basic gates, negative logic, 2-level/sum-of-products and multi-level digital design); combinational building blocks (multiplexers, demultiplexers, decoders); basic ripple-carry adder design; latches, flipflops and registers. A quick refresher on these topics will be included in the course. However, students with serious deficiencies should take an earlier course. No prior background on VHDL or VLSI circuits is required. If you have any questions about pre-requisites and your background, contact the instructor (nowick@cs.columbia.edu). REQUIRED TEXTBOOK: Stephen Brown and Zvonko Vranesic, "Fundamentals of Digital Logic with VHDL Design", **THIRD EDITION**, including Altera's Quartus II CAD System (on CD-ROM), McGraw-Hill, New York, NY. (Copies of the book will also be placed on reserve in the Engineering School Library.) The book will only be used for part of the course material. The course will include a number of additional handouts provided by the instructor, as well as recent research and industrial papers and articles. ---------------------------------------------------------------------------