Lisa K. Wu

New York, NY 10025

Education

PhD expected 2013, Computer Architecture, Columbia University

Research Advisor: Professor Martha Kim

MSCSE, Computer Architecture, University of Michigan  Ann Arbor

Research advisor: Professor Todd Austin

Masters thesis: Fast Flexible Architectures for Secure Communication

Created architecture for cryptography-algorithm-specific co-processor (VLIW): analyzed crypto benchmark characteristics, invented application-specific hardware, and evaluated performance/power/area in comparison to other state-or-the-art processors.

BSECE, Electrical and Computer Engineering, University of Illinois  Urbana Champaign

Employment

Research Assistant, Columbia University Computer Science Department, Present.

Computer Performance Architect, Compaq Corporation/Intel Corporation, Present.

Performance Engineer (Internship), Apple Computer, Inc.

Research Assistant, University of Michigan

Teaching Assistant, University of Michigan

Architecture Validation Engineer, Intel Corporation

Graduate Rotation Engineer, Intel Corporation

Network Engineer (Internship), Hewlett-Packard Company

Product Engineer (Co-op), Advanced Micro Devices, Inc.

Experience

Present

Graduate Research Assistant -- Columbia University -- New York, NY

•I am focusing on architectural research for abstract datatype instruction set and memory architectures that deliver better processor performance with less energy

Present

Computer Architect  -- Intel -- New York, NY/Portland, OR/Hudson, MA

MIC product design team

•Knights Corner Vector Processing Unit architect/Performance architect

•Larrabee Vector Processing Unit architect

Computer Performance Architect -- Compaq Corporation/Intel Corporation -- Hudson, MA

Next generation architecture and planning team

•Served as architecture representative to Intel’s Financial Services customers to understand workload characteristics, ensure Intel’s next generation X86 architecture meets customer needs, and answer any architectural/performance questions customers or business account representatives might have.

•Defined double-precision floating point microarchitecture for next generation X86 architecture.

X86 server product design team

•Led performance team for next generation X86 server microprocessor (code name BloomfieldMP): led a cross-site team consists of 6 microarchitects and performance engineers in Massachusetts and Barcelona and acquired 2 Intel fellows as internal consultants.

•Analyzed system performance bottlenecks for BloomfieldMP: set objectives for performance team, provided microarchitecture definition for various system components to performance team, reviewed performance data collected, quantitatively analyzed performance bottlenecks, proposed microarchitectural fixes, and presented results to senior management team(s).

•Led microarchitecture team for home protocol engine for BloomfieldMP: led a cross-functional team consists of 2 microarchitects, 1 implementer, and 2 validators through initial feasibility phase.

•Trained microarchitecture team members on cache coherence protocol and other microarchitectural details of the home protocol engine using white-board chalk talks.

•Proposed microarchitecture solutions to improve home protocol engine efficiency and quantitatively analyzed performance/power/area tradeoffs between different proposed microarchitecture solutions.

IPF server product design team

•Defined microarchitecture for instruction cache, instruction fetch, and instruction fill units for next generation IPF server microprocessor (code name Tanglewood): created MAS (Microprocessor Architecture Specification), wrote RTL (hardware description language similar to Verilog), simulated and debugged RTL models for functional and timing failures.

•Developed a skeleton performance model for Tanglewood using ASIM infrastructure (C++) starting from scratch and later on developed the front-end detailed performance model including instruction cache, fetch, fill, load score board, load miss replay, and other miscellaneous features. Served as liaison between the product development team and the performance team.

•Evaluated all microarchitectural design decisions in the front-end by quantitatively analyzing single-stream, multi-stream, and server workload performance including all levels of cache organization, fetch/fill algorithms, branch/way/index predictor algorithms, issue width, and various latency tradeoffs.

•Generated IPF traces for Spec workloads, developed performance projection methodology to compute SpecINT/SpecFP scores using weights, and correlated ASIM results with results from other Intel in-house performance models.

•Defined microarchitecture for performance monitor unit for Tanglewood: collaborated with various cross-site internal software/hardware teams to understand performance monitoring requirements.

•Performance validation for Tanglewood: supervised a PhD student intern, developed the BKM (Best Known Method) for performance validation, correlated performance from ASIM performance model with RTL model using various microbenchmarks, found performance bugs in instruction issue logic and proposed fixes.

Performance Engineer -- Apple Computer, Inc. -- Cupertino, CA

•Conducted performance studies on next generation architecture including microprocessors, Mac system components, and the Velocity Engine.

•Measured system bandwidth using performance monitors, quantitatively analyzed system bandwidth bottlenecks and communicated them to architects.

•Presented system bandwidth performance study results to external customers and internal senior management.

University of Michigan -- Ann Arbor, MI

•As a research assistant, I did architectural research on application-specific hardware; for details see publications listed below and masters thesis listed above.

•As a teaching assistant, I taught computer architecture class for first year graduate students. Class includes projects in simple-scalar performance simulator and Verilog.

Intel Corporation -- Portland, OR

•As a validation engineer on PentiumIV, I was responsible for full-chip pre-silicon functional debug and verification.

•As a validation engineer on PentiumIV, I developed test plan and wrote tests for FP/MMX/SSE multimedia instructions and various integer instructions.

•As a developer relations engineer on PentiumIII, I trained 3D game developers on Pentium III and Pentium II architectures and Intel-specific platform optimization to use SSE. I also managed account activities to ensure the launch of Pentium III was backed by design wins.

•As a developer relations engineer on PentiumIII, I modified ISV math kernels and vector libraries to use SSE, presented performance improvements to internal and external customers.

•As a performance architect on PentiumIII, I modified microbenchmarks to use SSE, did performance correlation using existing performance model, and analyzed anomalies between performance simulator and RTL simulator.

•As a chipset product engineer, I was responsible for modifications and maintenance of state equations used for post-silicon characterization and debugging.

Network Engineer -- Hewlett Packard Company -- Sunnyvale, CA

•Developed a $200K WAN test lab for business network solution services including proposal writing, pricing, and execution.

•Learned cgi and developed web pages for various HP internal hub sites.

Product Engineer -- Advanced Micro Devices, Inc. -- Austin, TX

•K5 microprocessor post-silicon debugging and characterization on Teradyne testers.

•Performance benchmarking of microprocessors and various system components using industry-standard benchmarks such as Winstone and Drystone.

•Designed bug tracking database for K5 using Lotus Notes database.