COMPUTER ARCHITECTURE December 3, 2002
COMPREHENSIVE EXAM INFORMATION
Day & Time and Location
Thursday December 19th, 2002 @ 1:10pm-4pm in 717 Hamilton Hall
Professor Tony Jebara, email@example.com
Dec. 5 4:30-6pm Dec. 16 3:00-4:30pm, Dec. 17 1:30-3pm or by appointment
Description: The exam will focus on the MIPS Architecture but explore the various concepts in CompOrg and CompArch including: digital logic, implementation of arithmetic logic unit, binary numbers, representation of negative numbers in a computer, floating point numbers, basic machine instructors for a MIPS RISC-type computer, assembly language programming, implementations of basic computer under various clocking assumptions, pipelining. Memory hierarchy: caches and virtual memory. In addition, Advanced Pipelining and Instruction Level Parallelism will be covered.
Texts: Topics from the following books will be covered. Note the specific chapters.
David A. Patterson and John L. Hennessy, Computer Organization and Design: the Hardware/Software Interface, Morgan Kaufmann, San Mateo, CA (1998). (2nd Edition):
CHAPTERS 1,2,3,4,5,6,7 and APPENDICES A,B.
John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, CA (1996). (2nd Edition)
BEYOND PATTERSON & HENNESSY CONCEPTS SO YOU ONLY
REALLY NEED TO READ CHAPTER 4.1-4.4 FROM H&P IN ADDITION…
Topics Covered in P&H:
•Ch.1: RISC/CISC, Stored-Program, 5-Parts, Hierarchy, bits
•Ch.2: Throughput, CPU Time, CPI, Arithmetic Mean, Geometric Mean, SPEC,
•Ch.3: Operands, Registers, MIPS Programming, Assembly, R,I,J-Types,
Pseudo-Instructions, Loops, Pointers, Stack, Functions, Caller-Callee
Conventions, ASCII Constant, Immediate, Addressing Styles, Link/Load
•Ch.4: Binary, 2’s Complement, Floating Point #’s Logic, Addition,
Subtraction, Overflow, Ripple-Carry ALU, Multiplication, Division
•Ch.5: Registers, Memory, Clocking, Single-Cycle Datapath, Control,
lw,sw,beq,R-type,j, Performance, Multi-Cycle Datapath, Control,
FSMs, MicroProgramming, Exceptions,
•Ch. 6: Pipelining, Hazards, Reordering Code, Pipelined Datapath, Control,
Data Hazards, Forwarding, Stalling, Branch Hazards, Prediction,
•Ch.7: Memory Hierarchy, Direct-Mapped Caches, Hits, Misses, MissRate,
Performance, Memory Design, Associative Caches, Multi-Level Caches,
Virtual Memory, Pages, Translation-Lookaside Buffer
•Appendices: SPIM, Digital Logic, Sequential, Clocks
Extra Topics Covered in H&P:
•Ch.4.1: Instruction Level Parallelism
•Ch.4.2: Overcoming Data Hazards with Dynamic Scheduling
•Ch.4.3: Reducing Branch Penalties with Dynamic Hardware Prediction
•Ch.4.4: Taking Advantage of More ILP with Multiple Issue
•Dec. 19th 1pm-4pm in Hamilton 717 (2:50 total time)
•About 7 large questions
•Mostly like homework questions & textbook questions
•Open book, open notes
•No calculators / PDAs / etc.
Web Page: The class URL is: http://www.cs.columbia.edu/~jebara/3824 and will contain copies of handouts, homework assignments, and other information. Course notes are available, come by my office. Solutions to homeworks are available outside my office in CEPSR 605 in a black file tray.