DATE: May 14, 2000 TO: Harold Weinreb CC: Joe Flicek, Mike Burke, Nita Younger, Jack Lacci FROM: Mike Keating, PPTI REF.: SIP Phone Development Status Report ------------------------------------------------------------------------------------------------------------- This document contains the findings of the "greenline" roadmap verification of the SIP PHONE 2.0 schematics against the printed circuit board artwork. Notes are also included as to the discrepancies with the prototype(s). Some of the notes simply address items that were most likely "embedded" into the intelligent PROTEL files but are not visible on the actual plotted schematics. The notes below do not address sheet one which is an overall interconnect sheet. All actual circuit connections are made on sheets 2 through 7. Schematic Sheet 2 1) U1 (TMS320C32) connections to ground (pins 8,12,15,16,19,21,22,35,36,39,46,50,51, 53,54,56,57,59,66,73,74,79,88,92,93,94,95,110,111,112,116,118,124,125,127,129,133, 135, and 136) not shown on schematic but connection made in artwork. These pins most likely feature a "not visible" attribute in the PROTEL files. PPT will either make these pins visible or include a table in the OrCAD version to aid in troubleshooting, etc. 2) U1 (TMS320C32) connections to Vcc (pins 15,16,85,86,90,102) not shown on schematic but connection made in artwork. These pins most likely feature a "not visible" attribute in the PROTEL files. PPT will either make these pins visible or include a table in the OrCAD version to aid in troubleshooting, etc. 3) Pin 8 of the J1 header is tied to ground in the artwork but the pin is clipped from the header. PPT will make this a no connect in the next version OrCAD schematics. Schematic Sheet 3 1) U3, U4, U5, U6, U7 do not show power pin connections for Vcc or GND. These pins most likely feature a "not visible" attribute in the PROTEL files. PPT will either make these pins visible or include a table in the OrCAD version to aid in troubleshooting, etc. Schematic Sheet 3 (continued from prior page) 2) The ROMOE signal from U7 pin 24 is also tied to J12 pin 9 but is given a different signal name called S_SOD. PPT plans on making this connection the same signal name (ROMOE) in the OrCAD version schematics. Schematic Sheet 4 1) U15 Altera EPM7128S connections to Vcc (pins 3, 13, 26, 38, 43, 53, 66, and 78) are not shown in the schematic but are connected in the circuit artwork. PPT will either make these pins visible or include a table in the OrCAD version to aid in troubleshooting, etc. 2) U15 Altera EPM7128S connections to GND (pins 7, 19, 26, 32, 42, 47, 59, 72, 82) are not shown in the schematic but are connected in the circuit artwork. PPT will either make these pins visible or include a table in the OrCAD version to aid in troubleshooting, etc. 3) Pin numbers are not present on the connections to the hook switch jack and alarm jack. PPT will include these in the next version OrCAD schematic. 4) The Optocoupler OPT0 (PS2701) is not installed on the board. Nor is the alarm connector J13. Should these parts be carried forward to the next version? Harold Weinreb, please advise. If they are carried forward, PPT will include the pin outs on the next version OrCAD schematic. *** Yes, we definitely want the optocoupler and alarm connector. 5) Connector SW1 HK (two pin jack) is not installed. Should this part be carried forward to the next version? Harold Weinreb, please advise. *** I assume this is the hook switch? Schematic Sheet 5 1) Connections to capacitors C48 and C49 are shown as going to ground in the schematic, however they are tied to EGND in the circuit artwork. PPT will correctly illustrate them going to EGND in the next version OrCAD schematic. 2) Pins 58, 59, and 60 on U8 AM79C940 are no connects and are not shown on the schematic although many other no connect pins are. PPT will include these into the next version schematic for consistency. 3) R30, C49, and L5 were not installed in the prototype. Harold Weinreb, please advise. Schematic Sheet 6 1) The pulldown resistors R24 and R25 that connect to the stereo jack J5 do not connect to the analog ground plane as shown in the schematic. The analog ground pin of the Jack J5 does not connect in the artwork either. PPT will verify these are connected in the next version circuit artwork. 2) The pin out numbers to the Mic jack J3 and the stereo jack J5 are not shown. PPT will add these to the next version OrCAD schematic. 3) Speaker Jack J6 is not installed. Should this be carried forward to the next version? Harold Weinreb, please advise Schematic Sheet 7 1) This sheet will be redone by PPT as it is based upon the LM7805/MAX787 regulators which caused the over temperature problem. Hal Weinreb asked that the LT1054CP and the LM79M05 be carried forward to the next version schematic (these parts are also omitted from the board). This negative five volt supply is understood by PPT to only be needed for use by the LCD. As the Optrex LCD DMC16433 is not on the present Optrex web page, PPT has contacted Apollo Display (Distributor for Optrex) in attempt to obtain specifications for the negative bias. PPT will then investigate a lower component count solution (i.e. a switched capacitor inverter such as the 7660) to provide the LCD bias. It is theorized that the present design for the -5V needed to be more robust to support the need of the Motorola CODEC that was originally utilized in the original version SIP.