CSEE W3827 - Fundamentals of Computer Systems

Call number 96898

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Course Information (Also available in pdf)

Professor Dan Rubenstein

Fall 2010

Contact Information
Who	Office	Phone	E-mail	Office Hours
Prof. Dan Rubenstein	CEPSR 816	(212) 854-0050	danr@cs.columbia.edu	M,W 2-3pm or by appt
TA Qi Ding	TA Room	(212) 854-4916	qd2110@columbia.edu	Th 3-5pm
TA Vinay Sharma	TA Room	(212) 854-4916	vs2330@columbia.edu	Tu 2-4pm
TA Cathy Chen	CEPSR 803	(212) 854-2900	cache@ee.columbia.edu	F 10am-12pm in CEPSR 8th fl Lounge
TA Yipeng Huang	TA Room	(212) 854-4916	yh2315@columbia.edu	MW 4:30-5:30pm

Course URL: http://wwww.cs.columbia.edu/~danr/3827
This course has a Discussion Board. Login via Courseworks to access it.
Course meeting time / location: 11:00 - 12:15 on T, Th in 627 Mudd
Pre-Requisites: An introductory programming course (e.g., COMS 1004 or 1007)
Description: This course explains, from a logic perspective, how computers work, i.e., how 0's and 1's are manipulated to do all the advanced calculations, computations, and services that computers can perform.
The first major topic is digital logic, which concerns the design of circuits to implement logic functions using standard components such as AND-gates, OR-gates, and inverters. The circuits might be used to control the flow of data within a computer, or the processing of the data (e.g., arithmetic operations), or to control the overall action of a computer. We will cover how to specify logic functions precisely, to manipulate formal expressions, and to implement them efficiently. We will then cover the design of basic building blocks, including the control, of modern digital computers. Both combinational and sequential circuits will be covered.
The second part of the course involves the structure and software interface of digital computers. Focusing our attention on modern RISC architecture. We will discuss the functional blocks such as the arithmetic unit, register files, and memory. Single-cycle and multiple-cycle implementations will be presented, followed by the concept of pipelining. We will cover the basics of caches and virtual memory. Machine and assembly language programming is a feature of the course. Main memory systems, currently DRAM, will be discussed as well as the operation of magnetic disk drives. Some aspects of I/O will also be introduced.
Note: This course is a joint CS/EE course.
Info on grading - click here
Two texts are required:
- Logic and Computer Design Fundamentals, 4th ed, by M. Morris Mano and Charles Kime, ISBN-10: 0-13-198926-X
  ISBN-13: 978-0-13-198926-9
- Computer Organization and Design, The Hardware/Software Interface, 4th ed, David A. Patterson and John L. Hennessy, Morgan Kaufmann, ISBN 978-0-12-374493-7
A text used in 2007 that can be used as a reference text:
- Fundamentals of Digital Logic with VHDL Design, 3rd ed, Stephen Brown and Zvonko Vranesic, McGraw-Hill,ISBN #0-07-352953-2 (ISBN13: 978-0-07-352953-0)
  (we actually used the 2nd edition 2 years ago: ISBN #0-07-249938-9)
Computing Accounts: not needed
Course Schedule: The schedule below is tentative - it is what we will target, but Prof. Rubenstein reserves the right to move ahead or behind, schedule to best accomodate the needs of the class (note that there are several "catchup" days to account for possibly falling behind.
Homework release dates and due dates will be altered as well to accommodate the pace of the class.

Date	#	Topics/chapters covered	Reading	Assigned	Due
9/7	1	Intro; Overview of Computer Architecture; Definitions (bit,byte,word)	M&K Ch 1
9/9	2	Binary number representations: 1's complement; 2's complement, adding and subtracting and overflow; floating point representations: overflow and underflow	M&K 4.3-4.4, 10.7, P&H 3.5 skip FP in MIPS	HW #1
9/14	3	Logic gates; XOR; Boolean Algebra; NAND and NOR gates; Taking complements; DeMorgan's Theorem; Duals	M&K 2.1-2.2, 2.8, 2.9
9/16	4	Standard Forms: minterms, maxterms, sum-of-products, product-of-sums	M&K 2.3	HW #2	HW #1
9/21	5	K-maps: simplification with implicants, Don't-care conditions	M&K 2.4-2.5
9/23	6	* Catchup *		HW #3	HW #2
9/28	7	Combinatorial Circuit Design: Multi-bit output functions; standard combinatorial circuits (enabler, decoder, encoder, priority encoder, mux	M&K 3.1, 3.3, 3, 3.6-3.9
9/30	8	Arithmetic funcs: Adder (half, full, ripple-carry, adder-subtractor); Contraction; Shifter	M&K 4.1-4.2, 4.5, 9.4	HW #4	HW #3
10/5	9	Sequential Circuitry: Latch, Flip-Flops, timing issues	M&K 5.1-5.3, 5.6
10/7	10	Sequential Circuit Analysis & Design: State machines	M&K 5.4-5.5	HW #5	HW #4
10/12	11	PLAs; ROM; Register Design: Load and Transfer	M&K 6.8, 7.1-7.3
10/14	12	Register Design cont'd: MicroOps and Counters, mux and serial transfer	M&K 7.5-7.6, 7.8-7.9		HW #5
10/19	13	* Catchup and/or Midterm review *
10/21	14	MIDTERM (in class)
10/26	15	Memory Design	M&K 8.1-8.7
10/28	16	Processor Design: Datapath, ALU	M&K 9.1-9.5	HW #6
11/2	--	ELECTION DAY - NO CLASS!
11/4	17	Control Word; Simple Arch; Instruction Decoder	M&K 9.6-9.8	HW #7	HW #6
11/9	18	Instruction Types and Formats	P&H 2.1-2.6
11/11	19	Branches, stacks, heaps, immediate addressing	P&H 2.7-2.8, 2.10	HW #8	HW #7
11/16	20	Single Cycle Datapath	P&H 4.1-4.4
11/18	21	Single Cycle Datapath cont'd		HW #9	HW #8
11/23	22	Pipelining	P&H 4.5-4.6
11/25	--	THANKSGIVING - NO CLASS!
11/30	23	Hazards	P&H 4.7-4.8
12/2	24	Cache & Cache Replacement Policies	P&H 5.1-5.2
12/7	25	* Catchup and/or review *			HW #9
12/9	26	* Catchup and/or review *
Tentative 12/21, 9am-12pm		FINAL EXAM:	Location TBD

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