CSEE E6861y: Readings

*"De Micheli" = Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, Mc-Graw Hill (1994).

Date assigned

Assigned Readings

Jan. 24

  • De Micheli, Preface + Chapter 1
  • Handout #5: The Quine-McCluskey Method
  • Lecture #1 Slides

Jan. 28

  • Handout #6: Multi-Output Functions (pp. 160-165)
  • Handout #7: Heuristic Minimization of Two-Level Circuits (pp. 185-191 top)
  • Handout #8: Rudell's PhD Thesis
    • read: abstract, ch. 1, ch. 2.1-2.4 (note: can skim defs. in 2.2 for multi-valued functions, but read others carefully), 2.8 intro. + 2.8.1, 2.9-2.11
  • Lecture #2 (pt. 1, pt. 2) slides

Feb. 7

  • De Micheli: ch. 7.1, ch. 7.2 (read pp. 270-276, skim 277-283), ch. 7.4.5
  • Handout #10: pp. 191-194 -- focus on Defs. 5.2.1-5.2.2; skim rest
  • Handout #11: read introduction, basic rules (B), miscellaneous rules (M)
  • Handout #12: read cofactor section only
  • Lecture #3 slides

Feb. 14

  • Handout #10: ch. 5.2-5.3 (we cover in a better order, and more systematically)
  • Handout #11: read remainder
  • Handout #12: read remainder *except* complementation sections
  • Handout #14: read 'solved problems' on single- and multi-output co-factor, tautology, unateness, etc.

Feb. 21

  • Handout #10: chs. 5.4, 5.6, 5.7
  • Handout #12: read remainder (complementation sections)
  • Handout #16: (fast complementation) read all
  • Handout #17 (optional): read/skim on last-gasp/super-gasp/make-sparse
  • Handout #18 (fast prime generation): read all
  • Handout #19 (prime generation example): read all
  • De Micheli (intro. to multi-level logic synthesis): read ch. 3.3.2, ch. 8.1-8.2
  • Lecture #5 slides

Feb. 28

  • De Micheli (intro. to multi-level logic synthesis): read ch. 8.3 pp. 360-364
  • Lecture #6 slides

March 7

  • Handout #22 (kernels/co-kernels/extraction): read all
  • De Micheli, ch. 8.3 (intro. to multi-level logic synthesis): read p. 365-top p. 370; read top p. 374-top p. 380
  • De Micheli, ch. 8.3 (intro. to multi-level logic synthesis): skim top p. 370-top p. 374 (we cover somewhat differently in Handout #22)
  • De Micheli, ch. 10.1-10.2 (technology mapping): read all

March 10

  • Handout #24 (basic tree-based covering [area-oriented]): read all
  • De Micheli, ch. 2.3.4 (dynamic programming): read pp. 49-51
  • De Micheli, ch. 10.3 (tech map basics): ch. 10.3, read only pp. 509-517
  • De Micheli, ch. 10.3 (tree-based covering): ch. 10.3, read only pp. 522-524 bottom

March 28

  • Handout #26 (advanced tree-based covering [delay-oriented, load-dependent]): read all
  • Handout #27 (advanced tree-based covering [power-oriented]): read abstract, secs. 1-3.3
  • Handout #27a (advanced tree-based covering [power-oriented]): read all (errata/clarifications on #27)
  • De Micheli, ch. 10.3 (tree-based covering): ch. 10.3, read bottom p. 524 - top p. 526
  • De Micheli, ch. 10.6 (perspectives): read all

April 4

  • Circuit Partitioning:
    • Handout #29: skim Abstract, sec. I; read/study sec. II, p. 93 - top left p. 95 (end of "Partitioning"); skim rest
    • Handout #30: read pp. 30-36, skim pp. 37-40

Apr. 11

  • Retiming:
    • De Micheli, ch. 9.3.1 Retiming, p. 462-bottom p. 469
    • Handout #32: Leiserson/Saxe, read Abstract and Section 1; read Sections 2-5 carefully (skip proofs; focus on concepts, theorems and algorithms)
    • Bellman-Ford algorithm: De Micheli, ch. 2.4.1, top p. 54-mid p. 57
    • Floyd-Warshall algorithm: you find (many resources available, incl. Wiki pages online)

Apr. 18

  • Retiming (additional reading for final project):
    • De Micheli, ch. 9.3.1 Retiming, bottom p. 469 - mid. p. 471 (skip from "Note that the timing feasibility problem" to end of section)
    • T.H. Cormen, C.E. Leiserson et al., "Introduction to Algorithms" (3rd edition) [digital access through Columbia libraries]: see Handout #33b for reading
  • Architectural (High-Level) Synthesis:
    • Handout #34: read all
    • DIFFEQ example: De Micheli, pp. 18-19
    • CDFG's: De Micheli, ch. 3.3.4, pp. 119-123 bottom
    • overview: De Micheli, ch. 4.1-4.2, ch. 4.3 (to end of 4.3.2)
    • Handout #36 (scheduling): read ch. 8.13-8.14, pp. 375-384

Apr. 25

  • Architectural (High-Level) Synthesis:
    • Handout #35 (resource sharing [variable/operation usage]): read ch. 8.4, bottom p. 336-top p. 342
    • Handout #35 (resource sharing [bus minimization]): skim ch. 8.4, top p. 342-top p. 343
  • Asynchronous Design:
    • Handout #37 (overview): read pp. 1-27, skim pp. 28-36
    • Handout #38 (hazard-free logic minimization): read slides 1-45




Last Updated: 4/25/13