CSEE W4823x: Readings

"B/V" = Brown/Vranesic, Fundamentals of Digial Logic with VHDL Design Third Edition ONLY

Date assigned

Assigned Readings

Sept. 4
  • B/V: Preface, ch. 1, ch. 2.9, ch. 4.11

Sept. 4 (optional)

Review/Background Reading:
  • basics of combinational logic: B/V ch. 2.1-2.8, 2.11-2.12
  • implementation technology: B/V ch. 3.1-3.5
  • combinational logic synthesis: B/V ch. 4.1-4.8, 4.13-4.14
  • Additionally, the Roth book (see full citation in Handout #1) is a good self-study guide and refresher resource for basic digital logic; it will be on reserve in the Monell Engineering Library.

Sept. 6
  • Handout #5: Quine-McCluskey Method
  • B/V: ch. 7.15: Timing Analysis of Flip-Flop Circuits
  • Lecture #2 Slides

Sept. 6 (optional)

Review/Background Reading:
  • latches, flipflops, basic registers: B/V ch. 7: introduction + ch. 7.1-7.9

Sept. 11
  • B/V: ch. 7.16-7.17 (incl. solved problems in ch 7.17)
  • Handout #6: pp. 737-740
  • Handout #7: pp. 62-65

Sept. 11 (optional)

Review/Background Reading:
  • B/V ch. 6: intro. + ch. 6.1-6.4
  • NOTE: see solved problems in B/V ch. 2.12, 4.14

Sept. 13
  • B/V ch. 8: intro. + 8.1-8.3
  • B/V ch. 8.5 (but skip 8.5.3)
  • B/V ch. 8.7 (note: B/V's "counter" is actually an FSM!)

Sept. 18
  • Handout #9
  • Lecture #5 Slides
  • B/V ch. 5 intro. + 5.1-5.3, ch. 5.8

Sept. 20
  • Handout #10 (Xilinx XC4000 Series FPGA's): read ch. 9.6 intro. + 9.6.1-9.6.2, skim 9.6.3-9.6.4
  • B/V, Appendix E.3: intro. + E.3.1 -- Altera Flex 10K FPGA's
  • B/V ch. 2.10 Introduction to VHDL
  • B/V ch. 4.12 VHDL basic circuit examples

Sept. 25
  • VHDL and arithmetic circuits: B/V ch. 5.5: intro + 5.5.1-5.5.3
  • (suggested: relevant parts of B/V VHDL appendix)

Sept. 25 (optional)

Review/Background Reading:
  • VHDL Reference: Bhasker ch. 2 -- on reserve
  • Wakerly book (VHDL section) -- on reserve

Sept. 30
  • Lecture #8 Slides
  • Handout #12: read all
  • Handout #13: read all
  • VHDL and arithmetic circuits: B/V ch. 5.5.4
  • VHDL for comb. circuits: B/V ch. 6.6: intro + 6.6.1-6.6.5, 6.6.8 (NOTE: skip sequential logic statements for now!)
  • Conclusions/Solved problems: B/V ch. 6.7-6.8

Sept. 27 (optional)

Review/Background Reading:
  • Recommended VHDL Reading: B/V Appendix A.1-A.7, A.11-A.12

Oct. 4
  • Analysis of sequential circuits: B/V ch. 8.9

Oct. 4 (optional)

Review/Background Reading:
  • Recommended Reading: 2's complement binary representation (already listed above): B/V ch. 5 intro. + 5.1-5.3
  • See also appropriate sections of Katz and Roth books (on reserve)

Oct. 5
  • Analysis of sequential circuits: B/V ch. 8.9
  • Lecture #10 Slides
  • Handout #15: pp. 17-24 only (carry-skip adders)
  • Handout #16: ch. 5.1 (RCA's) and ch. 5.2 (CLA's)

Oct. 9
  • Lecture #11 Slides (conditional sum adders)
  • Handout #15: Advanced Adders (Brunvand handout), (parallel prefix adders, etc.) read carefully -- pp. 1-16, p. 25 and pp. 43-46 (summary); skim rest
  • Handout #16: ch. 5.3 (conditional sum adders)
  • Handout #17: read all (conditional sum adders)
  • Handout #18: ch. 5.6 (parallel prefix adders)

Oct. 11
  • Handout #20: Combinational Multipliers, pp. 494-496
  • Combinational Multipliers: B/V ch. 5.6, ch. 5.9 (p. 311 only, using carry-save)
  • Handout #21: read abstract, sections 1-2, 6-7

Oct. 16
  • Handout #23: Read Abstract, sections I-II, section III (but skip/skim subsections on optimality and implementation), section V.

Oct. 18
  • Sequential VHDL ('sequential'/'behavioral'/using 'process' stmts.): B/V ch. 6.6.6-6.6.7, ch. 7.12-7.13, ch. 8.4-8.5

Oct. 18 (optional)

Review/Background Reading:
  • Recommended VHDL Reading: cover rest of B/V Appendix A = A.8-A.10

Oct. 23
  • Handout #26: ch 2.15, read all

Nov. 1
  • B/V ch. 8.10-8.13
  • B/V ch. 3.8 pp. 135-138 (buffers, tristate buffers)

Nov. 8
  • Handout #31: pp. 1-3
  • Handout #32: intro., ch. 8.1

Nov. 9
  • B/V ch. 5.7.2 Floating-Point Numbers
  • (recommended) Wiki "Floating Point" page (focus on "IEEE 754" section, skim rest)
  • (optional, on reserve in library) ch. 4.8, Floating-Point Representation and Operations, D. Patterson/J. Hennessy, "Computer Organization and Design" (2nd Edition)

Nov. 15
  • Handout #31: pp. 4-end
  • Handout #32: ch. 8.3 (but we will cover somewhat differently!)

Nov. 29
  • Handout #36: read all
  • Handout #37: read pp. 1-36, skim/skip rest
  • Handout #38: read all

Dec. 4
  • Handout #39: read pp. 1-44, 51-55, 62, 67 (skim rest)

Dec. 6
  • Handout #26: ch 2.15.5 Two-Dimensional (Product) Codes, read all [already assigned]
  • Handout #40: read through end of "Computation of CRC," skim rest
  • Handout #42: (NOTE: read #42 before #41) read secs. 1 and 3, skim sec. 2
  • Handout #41: read from bottom right p. 261 (Sequential and Combinational Logic Sensitivity) to top right p. 264 (up to Product Perspectives), skim rest



Last Updated: 12/6/2012