My research areas are
CAD algorithms, design methodologies for SoCs, formal verfication, and
embedded system design.
My research objective is to increase the
performance and quality of hardware and
software systems, and to make the design and implementations
efficient and error-free.
Current Projects
Performance Improvement of Latency-Insensitive Design
The goal of this project is to optimize performance of
latency-insensitive systems by exploiting the individual features of white-
box processing cores and by deriving novel algorithms for throughput-oriented
system floorplanning. The overall goal of this research is to improve
the performance of a latency-insensitive system in terms of average
data processing throughput without violating possible "tight latency constraints" among its
components.
The technique based on the characteristics of separate
processing cores is motivated by the observation that a component
does not need to be stalled if an
incoming void data token is not necessary for the current computation
(thus the token is a don't care).
The initial results show that this DC-based speed-up is promising, and can
be achieved with little hardware overhead.
Throughput-driven physical design provides another avenue to improve
system performance.
By careful floorplanning and placing components
one can avoid throughput penalties induced by using relay stations to
accommodate communication delays. However, this opportunity has not
been fully taken by state-of-the-art physical design
tools.
Code Compression for Embedded Systems
I am also working on code compression for embedded
systems. I developed an architecture-oriented compression framework
for embedded microprocessors, which achieves the best program
compressions on ARM processors without any modification to compiler
tools. I also discovered a new, low-overhead
multiple
Huffman coding
technique, called curve-fitting Huffman code, and various
efficient state- and
context-based higher-order models.
Currently I am working on techniques to
automatically construct higher-order models, and applying the
framework to a wider range of microprocessors.
Past Projects
Synthesis of Control Policies
for Controlled Petri Nets
My master thesis focused on synthesis of control policies
for controlled Petri nets. A controlled Petri net is used to model a
discrete event system, in which a control policy is sought to
guarantee certain desirable properties. In this work I developed a novel
synthesis technique using
model checking technique based on temporal logic
to guide the synthesis process. This method went beyond the limit of
traditional synthesizers: one can find a policy ensuring any property
expressible in the temporal logic.