Chip Multiprocessors (CMP) enhanced with Thread-Level Speculation (TLS) are promising platforms to speed-up sequential applications. However, for TLS to deliver on its promise, architecture and compiler must support flexible task structures that exploit multiple sources of speculative parallelism. Additionally, speculative tasking must be shown to be sufficiently energy efficient to compete against conventional superscalars.

In this talk, I will describe TLS CMP designs that both deliver high performance and are energy efficient. High performance is accomplished with novel micro-architecture mechanisms and compilation transformations that fundamentally enable flexible task structures, such as any nesting of subroutines and loop iterations. I will also challenge the commonly-held view that TLS consumes excessive energy. Our TLS CMP is not only faster but also more energy efficient than a state-of-the-art wide-issue superscalar. I will identify the sources of energy consumption in TLS, and propose energy-centric optimizations that mitigate them.

Taken together, these contributions make TLS CMPs attractive platforms for general-purpose applications.

Bio:

Jose Renau is a Ph.D. candidate at the University of Illinois at Urbana-Champaign. He expects to finish his Ph.D in the summer of 2004.